diff mbox

[4/8] tests: Better handle legacy IO addresses in tco-test

Message ID 1476787933-7180-5-git-send-email-david@gibson.dropbear.id.au (mailing list archive)
State New, archived
Headers show

Commit Message

David Gibson Oct. 18, 2016, 10:52 a.m. UTC 
tco_test uses the libqos PCI code to access the device.  This makes perfect
sense for the PCI config space accesses.  However for IO, rather than the
usual PCI approach of mapping a PCI BAR, then accessing that, it instead
uses the legacy approach of fixed, known addresses in PCI IO space.

That doesn't work very well with the qpci_io_{read,write} functions because
we never use qpci_iomap() and so have to make assumptions about the
internal encoding of the address tokens iomap() returns.

This patch avoids that, by directly using the bus's pio_{read,write}
callbacks, which are defined to take addresses within the PCI IO space.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 tests/tco-test.c | 87 ++++++++++++++++++++++++++++----------------------------
 1 file changed, 44 insertions(+), 43 deletions(-)

Comments

Laurent Vivier Oct. 18, 2016, 3:14 p.m. UTC | #1 
On 18/10/2016 12:52, David Gibson wrote:
> tco_test uses the libqos PCI code to access the device.  This makes perfect
> sense for the PCI config space accesses.  However for IO, rather than the
> usual PCI approach of mapping a PCI BAR, then accessing that, it instead
> uses the legacy approach of fixed, known addresses in PCI IO space.
> 
> That doesn't work very well with the qpci_io_{read,write} functions because
> we never use qpci_iomap() and so have to make assumptions about the
> internal encoding of the address tokens iomap() returns.
> 
> This patch avoids that, by directly using the bus's pio_{read,write}
> callbacks, which are defined to take addresses within the PCI IO space.
> 
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>  tests/tco-test.c | 87 ++++++++++++++++++++++++++++----------------------------
>  1 file changed, 44 insertions(+), 43 deletions(-)
> 
> diff --git a/tests/tco-test.c b/tests/tco-test.c
> index 0d201b1..e668630 100644
> --- a/tests/tco-test.c
> +++ b/tests/tco-test.c
> @@ -40,13 +40,13 @@ enum {
>  typedef struct {
>      const char *args;
>      bool noreboot;
> +    QPCIBus *bus;
>      QPCIDevice *dev;
> -    void *tco_io_base;
> +    uint16_t tco_io_base;
>  } TestData;
>  
>  static void test_init(TestData *d)
>  {
> -    QPCIBus *bus;
>      QTestState *qs;
>      char *s;
>  
> @@ -57,8 +57,8 @@ static void test_init(TestData *d)
>      qtest_irq_intercept_in(qs, "ioapic");
>      g_free(s);
>  
> -    bus = qpci_init_pc(NULL);
> -    d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
> +    d->bus = qpci_init_pc(NULL);

You can use qtest_pc_boot() now.

> +    d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
>      g_assert(d->dev != NULL);
>  
>      qpci_device_enable(d->dev);
> @@ -70,42 +70,42 @@ static void test_init(TestData *d)
>      /* set Root Complex BAR */
>      qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
>  
> -    d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
> +    d->tco_io_base = PM_IO_BASE_ADDR + 0x60;

Why don't you use QPCIBar in TestData to store the address?
And you can call qpci_io_XXX() with it.

Thanks,
Laurent
Laurent Vivier Oct. 18, 2016, 4:28 p.m. UTC | #2 
On 18/10/2016 17:14, Laurent Vivier wrote:
> 
> 
> On 18/10/2016 12:52, David Gibson wrote:
>> tco_test uses the libqos PCI code to access the device.  This makes perfect
>> sense for the PCI config space accesses.  However for IO, rather than the
>> usual PCI approach of mapping a PCI BAR, then accessing that, it instead
>> uses the legacy approach of fixed, known addresses in PCI IO space.
>>
>> That doesn't work very well with the qpci_io_{read,write} functions because
>> we never use qpci_iomap() and so have to make assumptions about the
>> internal encoding of the address tokens iomap() returns.
>>
>> This patch avoids that, by directly using the bus's pio_{read,write}
>> callbacks, which are defined to take addresses within the PCI IO space.
>>
>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>>  tests/tco-test.c | 87 ++++++++++++++++++++++++++++----------------------------
>>  1 file changed, 44 insertions(+), 43 deletions(-)
>>
>> diff --git a/tests/tco-test.c b/tests/tco-test.c
>> index 0d201b1..e668630 100644
>> --- a/tests/tco-test.c
>> +++ b/tests/tco-test.c
>> @@ -40,13 +40,13 @@ enum {
>>  typedef struct {
>>      const char *args;
>>      bool noreboot;
>> +    QPCIBus *bus;
>>      QPCIDevice *dev;
>> -    void *tco_io_base;
>> +    uint16_t tco_io_base;
>>  } TestData;
>>  
>>  static void test_init(TestData *d)
>>  {
>> -    QPCIBus *bus;
>>      QTestState *qs;
>>      char *s;
>>  
>> @@ -57,8 +57,8 @@ static void test_init(TestData *d)
>>      qtest_irq_intercept_in(qs, "ioapic");
>>      g_free(s);
>>  
>> -    bus = qpci_init_pc(NULL);
>> -    d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
>> +    d->bus = qpci_init_pc(NULL);
> 
> You can use qtest_pc_boot() now.
> 
>> +    d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
>>      g_assert(d->dev != NULL);
>>  
>>      qpci_device_enable(d->dev);
>> @@ -70,42 +70,42 @@ static void test_init(TestData *d)
>>      /* set Root Complex BAR */
>>      qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
>>  
>> -    d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
>> +    d->tco_io_base = PM_IO_BASE_ADDR + 0x60;
> 
> Why don't you use QPCIBar in TestData to store the address?
> And you can call qpci_io_XXX() with it.

OK, I was watching the state of qpci_io_XXX() after the series, so you
can't do that here, but perhaps this patch should be moved to PATCH 8/8?

Laurent
David Gibson Oct. 19, 2016, 3:09 a.m. UTC | #3 
On Tue, Oct 18, 2016 at 05:14:04PM +0200, Laurent Vivier wrote:
> 
> 
> On 18/10/2016 12:52, David Gibson wrote:
> > tco_test uses the libqos PCI code to access the device.  This makes perfect
> > sense for the PCI config space accesses.  However for IO, rather than the
> > usual PCI approach of mapping a PCI BAR, then accessing that, it instead
> > uses the legacy approach of fixed, known addresses in PCI IO space.
> > 
> > That doesn't work very well with the qpci_io_{read,write} functions because
> > we never use qpci_iomap() and so have to make assumptions about the
> > internal encoding of the address tokens iomap() returns.
> > 
> > This patch avoids that, by directly using the bus's pio_{read,write}
> > callbacks, which are defined to take addresses within the PCI IO space.
> > 
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> >  tests/tco-test.c | 87 ++++++++++++++++++++++++++++----------------------------
> >  1 file changed, 44 insertions(+), 43 deletions(-)
> > 
> > diff --git a/tests/tco-test.c b/tests/tco-test.c
> > index 0d201b1..e668630 100644
> > --- a/tests/tco-test.c
> > +++ b/tests/tco-test.c
> > @@ -40,13 +40,13 @@ enum {
> >  typedef struct {
> >      const char *args;
> >      bool noreboot;
> > +    QPCIBus *bus;
> >      QPCIDevice *dev;
> > -    void *tco_io_base;
> > +    uint16_t tco_io_base;
> >  } TestData;
> >  
> >  static void test_init(TestData *d)
> >  {
> > -    QPCIBus *bus;
> >      QTestState *qs;
> >      char *s;
> >  
> > @@ -57,8 +57,8 @@ static void test_init(TestData *d)
> >      qtest_irq_intercept_in(qs, "ioapic");
> >      g_free(s);
> >  
> > -    bus = qpci_init_pc(NULL);
> > -    d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
> > +    d->bus = qpci_init_pc(NULL);
> 
> You can use qtest_pc_boot() now.

I could, but that's not really in scope for this patch.

> > +    d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
> >      g_assert(d->dev != NULL);
> >  
> >      qpci_device_enable(d->dev);
> > @@ -70,42 +70,42 @@ static void test_init(TestData *d)
> >      /* set Root Complex BAR */
> >      qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
> >  
> > -    d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
> > +    d->tco_io_base = PM_IO_BASE_ADDR + 0x60;
> 
> Why don't you use QPCIBar in TestData to store the address?
> And you can call qpci_io_XXX() with it.

As noted in your later patch, QPCIBar hasn't been introduced at this
stage of the series.  Further, storing the address in there would
require the testcase to understand the QPCIBar's internal structure,
which is exactly what I'm trying to avoid.

Now, it's quite likely that the ICH9 device here has the same
registers aliased in a PIO bar, which we could map in the normal way.
However, if we did that, we wouldn't be testing quite the same thing -
we'd be testing availability of the registers via the BAR address,
rather than via the fixed legacy address.
David Gibson Oct. 19, 2016, 3:19 a.m. UTC | #4 
On Tue, Oct 18, 2016 at 06:28:26PM +0200, Laurent Vivier wrote:
> 
> 
> On 18/10/2016 17:14, Laurent Vivier wrote:
> > 
> > 
> > On 18/10/2016 12:52, David Gibson wrote:
> >> tco_test uses the libqos PCI code to access the device.  This makes perfect
> >> sense for the PCI config space accesses.  However for IO, rather than the
> >> usual PCI approach of mapping a PCI BAR, then accessing that, it instead
> >> uses the legacy approach of fixed, known addresses in PCI IO space.
> >>
> >> That doesn't work very well with the qpci_io_{read,write} functions because
> >> we never use qpci_iomap() and so have to make assumptions about the
> >> internal encoding of the address tokens iomap() returns.
> >>
> >> This patch avoids that, by directly using the bus's pio_{read,write}
> >> callbacks, which are defined to take addresses within the PCI IO space.
> >>
> >> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> >> ---
> >>  tests/tco-test.c | 87 ++++++++++++++++++++++++++++----------------------------
> >>  1 file changed, 44 insertions(+), 43 deletions(-)
> >>
> >> diff --git a/tests/tco-test.c b/tests/tco-test.c
> >> index 0d201b1..e668630 100644
> >> --- a/tests/tco-test.c
> >> +++ b/tests/tco-test.c
> >> @@ -40,13 +40,13 @@ enum {
> >>  typedef struct {
> >>      const char *args;
> >>      bool noreboot;
> >> +    QPCIBus *bus;
> >>      QPCIDevice *dev;
> >> -    void *tco_io_base;
> >> +    uint16_t tco_io_base;
> >>  } TestData;
> >>  
> >>  static void test_init(TestData *d)
> >>  {
> >> -    QPCIBus *bus;
> >>      QTestState *qs;
> >>      char *s;
> >>  
> >> @@ -57,8 +57,8 @@ static void test_init(TestData *d)
> >>      qtest_irq_intercept_in(qs, "ioapic");
> >>      g_free(s);
> >>  
> >> -    bus = qpci_init_pc(NULL);
> >> -    d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
> >> +    d->bus = qpci_init_pc(NULL);
> > 
> > You can use qtest_pc_boot() now.
> > 
> >> +    d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
> >>      g_assert(d->dev != NULL);
> >>  
> >>      qpci_device_enable(d->dev);
> >> @@ -70,42 +70,42 @@ static void test_init(TestData *d)
> >>      /* set Root Complex BAR */
> >>      qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
> >>  
> >> -    d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
> >> +    d->tco_io_base = PM_IO_BASE_ADDR + 0x60;
> > 
> > Why don't you use QPCIBar in TestData to store the address?
> > And you can call qpci_io_XXX() with it.
> 
> OK, I was watching the state of qpci_io_XXX() after the series, so you
> can't do that here, but perhaps this patch should be moved to PATCH 8/8?

No, this is quite deliberately before 8/8.  The point of 8/8 is that
QPCIBar is supposed to be opaque to the tests/drivers.  Using the
legacy addresses requires that the test/driver work directly with the
actual IO address.  Mixing the two - having the test case construct
the base pointer makes the conversion to an opaque token more awkward.

However.. another approach just occurred to me.  I could define a
special QPCIBar constant - exported as a global by libqos, or returned
by a function - which references the legacy PIO space instead of a
particular bar.  The qpci_io_*() functions could be used with that.

I'll look into that, and see how it works.
diff mbox

Patch

diff --git a/tests/tco-test.c b/tests/tco-test.c
index 0d201b1..e668630 100644
--- a/tests/tco-test.c
+++ b/tests/tco-test.c
@@ -40,13 +40,13 @@  enum {
 typedef struct {
     const char *args;
     bool noreboot;
+    QPCIBus *bus;
     QPCIDevice *dev;
-    void *tco_io_base;
+    uint16_t tco_io_base;
 } TestData;
 
 static void test_init(TestData *d)
 {
-    QPCIBus *bus;
     QTestState *qs;
     char *s;
 
@@ -57,8 +57,8 @@  static void test_init(TestData *d)
     qtest_irq_intercept_in(qs, "ioapic");
     g_free(s);
 
-    bus = qpci_init_pc(NULL);
-    d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
+    d->bus = qpci_init_pc(NULL);
+    d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
     g_assert(d->dev != NULL);
 
     qpci_device_enable(d->dev);
@@ -70,42 +70,42 @@  static void test_init(TestData *d)
     /* set Root Complex BAR */
     qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
 
-    d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
+    d->tco_io_base = PM_IO_BASE_ADDR + 0x60;
 }
 
 static void stop_tco(const TestData *d)
 {
     uint32_t val;
 
-    val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
+    val = d->bus->pio_readw(d->bus, d->tco_io_base + TCO1_CNT);
     val |= TCO_TMR_HLT;
-    qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
+    d->bus->pio_writew(d->bus, d->tco_io_base + TCO1_CNT, val);
 }
 
 static void start_tco(const TestData *d)
 {
     uint32_t val;
 
-    val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
+    val = d->bus->pio_readw(d->bus, d->tco_io_base + TCO1_CNT);
     val &= ~TCO_TMR_HLT;
-    qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
+    d->bus->pio_writew(d->bus, d->tco_io_base + TCO1_CNT, val);
 }
 
 static void load_tco(const TestData *d)
 {
-    qpci_io_writew(d->dev, d->tco_io_base + TCO_RLD, 4);
+    d->bus->pio_writew(d->bus, d->tco_io_base + TCO_RLD, 4);
 }
 
 static void set_tco_timeout(const TestData *d, uint16_t ticks)
 {
-    qpci_io_writew(d->dev, d->tco_io_base + TCO_TMR, ticks);
+    d->bus->pio_writew(d->bus, d->tco_io_base + TCO_TMR, ticks);
 }
 
 static void clear_tco_status(const TestData *d)
 {
-    qpci_io_writew(d->dev, d->tco_io_base + TCO1_STS, 0x0008);
-    qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0002);
-    qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0004);
+    d->bus->pio_writew(d->bus, d->tco_io_base + TCO1_STS, 0x0008);
+    d->bus->pio_writew(d->bus, d->tco_io_base + TCO2_STS, 0x0002);
+    d->bus->pio_writew(d->bus, d->tco_io_base + TCO2_STS, 0x0004);
 }
 
 static void reset_on_second_timeout(bool enable)
@@ -128,25 +128,25 @@  static void test_tco_defaults(void)
     d.args = NULL;
     d.noreboot = true;
     test_init(&d);
-    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD), ==,
+    g_assert_cmpint(d.bus->pio_readw(d.bus, d.tco_io_base + TCO_RLD), ==,
                     TCO_RLD_DEFAULT);
     /* TCO_DAT_IN & TCO_DAT_OUT */
-    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_DAT_IN), ==,
+    g_assert_cmpint(d.bus->pio_readw(d.bus, d.tco_io_base + TCO_DAT_IN), ==,
                     (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
     /* TCO1_STS & TCO2_STS */
-    g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_STS), ==,
+    g_assert_cmpint(d.bus->pio_readl(d.bus, d.tco_io_base + TCO1_STS), ==,
                     (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
     /* TCO1_CNT & TCO2_CNT */
-    g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_CNT), ==,
+    g_assert_cmpint(d.bus->pio_readl(d.bus, d.tco_io_base + TCO1_CNT), ==,
                     (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
     /* TCO_MESSAGE1 & TCO_MESSAGE2 */
-    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_MESSAGE1), ==,
+    g_assert_cmpint(d.bus->pio_readw(d.bus, d.tco_io_base + TCO_MESSAGE1), ==,
                     (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
-    g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + TCO_WDCNT), ==,
+    g_assert_cmpint(d.bus->pio_readb(d.bus, d.tco_io_base + TCO_WDCNT), ==,
                     TCO_WDCNT_DEFAULT);
-    g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + SW_IRQ_GEN), ==,
+    g_assert_cmpint(d.bus->pio_readb(d.bus, d.tco_io_base + SW_IRQ_GEN), ==,
                     SW_IRQ_GEN_DEFAULT);
-    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_TMR), ==,
+    g_assert_cmpint(d.bus->pio_readw(d.bus, d.tco_io_base + TCO_TMR), ==,
                     TCO_TMR_DEFAULT);
     qtest_end();
 }
@@ -171,23 +171,23 @@  static void test_tco_timeout(void)
     clock_step(ticks * TCO_TICK_NSEC);
 
     /* test first timeout */
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_STS);
     ret = val & TCO_TIMEOUT ? 1 : 0;
     g_assert(ret == 1);
 
     /* test clearing timeout bit */
     val |= TCO_TIMEOUT;
-    qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
+    d.bus->pio_writew(d.bus, d.tco_io_base + TCO1_STS, val);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_STS);
     ret = val & TCO_TIMEOUT ? 1 : 0;
     g_assert(ret == 0);
 
     /* test second timeout */
     clock_step(ticks * TCO_TICK_NSEC);
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_STS);
     ret = val & TCO_TIMEOUT ? 1 : 0;
     g_assert(ret == 1);
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO2_STS);
     ret = val & TCO_SECOND_TO_STS ? 1 : 0;
     g_assert(ret == 1);
 
@@ -214,13 +214,13 @@  static void test_tco_max_timeout(void)
     start_tco(&d);
     clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
 
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO_RLD);
     g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_STS);
     ret = val & TCO_TIMEOUT ? 1 : 0;
     g_assert(ret == 0);
     clock_step(TCO_TICK_NSEC);
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_STS);
     ret = val & TCO_TIMEOUT ? 1 : 0;
     g_assert(ret == 1);
 
@@ -358,11 +358,12 @@  static void test_tco_ticks_counter(void)
     start_tco(&d);
 
     do {
-        rld = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD) & TCO_RLD_MASK;
+        rld = d.bus->pio_readw(d.bus, d.tco_io_base + TCO_RLD) & TCO_RLD_MASK;
         g_assert_cmpint(rld, ==, ticks);
         clock_step(TCO_TICK_NSEC);
         ticks--;
-    } while (!(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS) & TCO_TIMEOUT));
+    } while (!(d.bus->pio_readw(d.bus,
+                                d.tco_io_base + TCO1_STS) & TCO_TIMEOUT));
 
     stop_tco(&d);
     qtest_end();
@@ -378,10 +379,10 @@  static void test_tco1_control_bits(void)
     test_init(&d);
 
     val = TCO_LOCK;
-    qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
+    d.bus->pio_writew(d.bus, d.tco_io_base + TCO1_CNT, val);
     val &= ~TCO_LOCK;
-    qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
-    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_CNT), ==,
+    d.bus->pio_writew(d.bus, d.tco_io_base + TCO1_CNT, val);
+    g_assert_cmpint(d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_CNT), ==,
                     TCO_LOCK);
     qtest_end();
 }
@@ -405,13 +406,13 @@  static void test_tco1_status_bits(void)
     start_tco(&d);
     clock_step(ticks * TCO_TICK_NSEC);
 
-    qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_IN, 0);
-    qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_OUT, 0);
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
+    d.bus->pio_writeb(d.bus, d.tco_io_base + TCO_DAT_IN, 0);
+    d.bus->pio_writeb(d.bus, d.tco_io_base + TCO_DAT_OUT, 0);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_STS);
     ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
     g_assert(ret == 1);
-    qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
-    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS), ==, 0);
+    d.bus->pio_writew(d.bus, d.tco_io_base + TCO1_STS, val);
+    g_assert_cmpint(d.bus->pio_readw(d.bus, d.tco_io_base + TCO1_STS), ==, 0);
     qtest_end();
 }
 
@@ -434,11 +435,11 @@  static void test_tco2_status_bits(void)
     start_tco(&d);
     clock_step(ticks * TCO_TICK_NSEC * 2);
 
-    val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
+    val = d.bus->pio_readw(d.bus, d.tco_io_base + TCO2_STS);
     ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
     g_assert(ret == 1);
-    qpci_io_writew(d.dev, d.tco_io_base + TCO2_STS, val);
-    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS), ==, 0);
+    d.bus->pio_writew(d.bus, d.tco_io_base + TCO2_STS, val);
+    g_assert_cmpint(d.bus->pio_readw(d.bus, d.tco_io_base + TCO2_STS), ==, 0);
     qtest_end();
 }