[03/16] target-m68k: add exg ops

Commit Message

Laurent Vivier Oct. 26, 2016, 4:35 p.m. UTC

Signed-off-by: Laurent Vivier <[e-mail]>
---
 target-m68k/translate.c | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

Comments

Richard Henderson Oct. 26, 2016, 10:07 p.m. UTC | #1

On 10/26/2016 09:35 AM, Laurent Vivier wrote:
> +    INSN(undef,     c140, f1f8, CF_ISA_A);
> +    INSN(exg,       c140, f1f8, M68000);
> +    INSN(undef,     c148, f1f8, CF_ISA_A);
> +    INSN(exg,       c148, f1f8, M68000);
> +    INSN(undef,     c188, f1f8, CF_ISA_A);
> +    INSN(exg,       c188, f1f8, M68000);

Given that we started with

+    BASE(undef,     0000, 0000);

why do we need to re-add these undef's?

Otherwise, why not use these, and a helper, to avoid having to re-decode.

static void do_exg(TCGv reg1, TCGv reg2)
{
     TCGv temp = tcg_temp_new();
     tcg_gen_mov_i32(temp, reg1);
     tcg_gen_mov_i32(reg1, reg2);
     tcg_gen_mov_i32(reg2, temp);
     tcg_temp_free(temp);
}

DISAS_INSN(exg_dd)
{
     do_exg(DREG(insn, 9), DREG(insn, 0));
}

DISAS_INSN(exg_aa)
{
     do_exg(AREG(insn, 9), AREG(insn, 0));
}

DISAS_INSN(exg_da)
{
     do_exg(DREG(insn, 9), AREG(insn, 0));
}


r~

Patch

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 0d3111d..a07b6f5 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2021,6 +2021,41 @@  DISAS_INSN(eor)
     DEST_EA(env, insn, OS_LONG, dest, &addr);
 }
 
+DISAS_INSN(exg)
+{
+    TCGv src;
+    TCGv reg;
+    TCGv dest;
+    int exg_mode;
+
+    exg_mode = insn & 0x1f8;
+
+    dest = tcg_temp_new();
+    switch (exg_mode) {
+    case 0x140:
+        /* exchange Dx and Dy */
+        src = DREG(insn, 9);
+        reg = DREG(insn, 0);
+        break;
+    case 0x148:
+        /* exchange Ax and Ay */
+        src = AREG(insn, 9);
+        reg = AREG(insn, 0);
+        break;
+    case 0x188:
+        /* exchange Dx and Ay */
+        src = DREG(insn, 9);
+        reg = AREG(insn, 0);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    tcg_gen_mov_i32(dest, src);
+    tcg_gen_mov_i32(src, reg);
+    tcg_gen_mov_i32(reg, dest);
+    tcg_temp_free(dest);
+}
+
 DISAS_INSN(and)
 {
     TCGv src;
@@ -3154,6 +3189,12 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(cmpa,      b0c0, f0c0, M68000);
     INSN(eor,       b180, f1c0, CF_ISA_A);
     BASE(and,       c000, f000);
+    INSN(undef,     c140, f1f8, CF_ISA_A);
+    INSN(exg,       c140, f1f8, M68000);
+    INSN(undef,     c148, f1f8, CF_ISA_A);
+    INSN(exg,       c148, f1f8, M68000);
+    INSN(undef,     c188, f1f8, CF_ISA_A);
+    INSN(exg,       c188, f1f8, M68000);
     BASE(mulw,      c0c0, f0c0);
     BASE(addsub,    d000, f000);
     INSN(addx,      d180, f1f8, CF_ISA_A);