From patchwork Thu Oct 27 19:09:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 9400235 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 170D16057E for ; Thu, 27 Oct 2016 19:14:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA68A2A38A for ; Thu, 27 Oct 2016 19:14:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DF6592A38C; Thu, 27 Oct 2016 19:14:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 316812A38A for ; Thu, 27 Oct 2016 19:14:14 +0000 (UTC) Received: from localhost ([::1]:44047 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzq7x-0005f9-F8 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 27 Oct 2016 15:14:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzq4B-0002jt-F0 for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzq48-0001KB-Sw for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:19 -0400 Received: from mout.kundenserver.de ([217.72.192.73]:53256) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bzq48-0001JW-GP for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:16 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue101) with ESMTPSA (Nemesis) id 0LheYD-1cdriq0Kcj-00mwDA; Thu, 27 Oct 2016 21:10:01 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 27 Oct 2016 21:09:53 +0200 Message-Id: <1477595394-23807-3-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477595394-23807-1-git-send-email-laurent@vivier.eu> References: <1477595394-23807-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:3jDpoVPoCbQJbT6azjJxo27bDIlj60IFqzTOqtSOW1jR+M/l4Ev eOXnYA2Ogj4mb4N/A8duxS8lhST0kTsUDokVI1TueE7T7d9gCG/lntjAfda/mTIYBeqcA9v MariANymFYd4bRfewtJntwoHSM6SMxGzbL3nRfznAt2O1PpENmdWwzUX3RjKd0pZBh4NbHv QyT5TsAwpJl4EAzh8l6WA== X-UI-Out-Filterresults: notjunk:1; V01:K0:pZjSqIvFFg0=:aN/yKDdfKd9GiH6OBs+4LB ZyP8UpiWc+1MZx82RNZfSmvAdzEaBkN0+WgwzhN7DxZfZ4AsJ7R3SKrPItZarbdVM+z0C0yg/ U2P+8ggjEAOF3TqpgY3mtwOlBB02nco8hgDQk4Emac/RX2u6hI3WUuQv9FpEBnxky8Hmov4ST scB/EeFAIIY0poWF19iblNULFUzsa6bxfxA9vYbklVf0siAJ/fdOuzDbCOElsbjhN3b/cz9UO 6dbRXm53PUs84qzuL/s0kVcEZQXfaOCMCwKdYhziUo0Mdty+Yn4iD2I2pCsWg5fORpB+EuCGx HHH7jCr5mYYPCG/osL8NAlN0AzVdIMUWC6Sna5q2I8f1YkYzkNRlrJXqsG3c4vqff3PqZNXlq nXLyjRFPko3PROyxxWehpZ34WjRo6M/ap1Fkk1QArEJidR1JGnkxpP2YiOLfpJkfZJN7HZrNt zP6+Wk5GZabIvXpGrfZeoLK6p4y37+MFTlTcbJEpBSJV4sL4E2hKekN0N8mu5J3zl20VhIckJ A7TAOCs92rXAye1rVZowm9dQVfk70Aejj54w7pqcpLEhJ82zwGEnSGnx8LmxmfeStfsKbBOKe pzZgQiEbSdYbVHCba3LKy8Ln5zT7H30jskA8EkBqoKv7Zja9QDTOzDMrT1+5HPOzZcxaiGFrD 1rZjpcv8YdNso/dTzUWEkb/NKd3msZeAHShyvTCD7DQ3NbcvUJ9w6rn3x15t7Sl47uV4= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.72.192.73 Subject: [Qemu-devel] [PATCH 2/3] target-m68k: Inline shifts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Henderson Original patch from Richard Henderson Fix arithmetical/logical switch Signed-off-by: Laurent Vivier --- target-m68k/helper.c | 52 --------------------------- target-m68k/helper.h | 3 -- target-m68k/translate.c | 96 +++++++++++++++++++++++++++++++++++++------------ 3 files changed, 73 insertions(+), 78 deletions(-) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 7aed9ff..f750d3d 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -284,58 +284,6 @@ void HELPER(set_sr)(CPUM68KState *env, uint32_t val) m68k_switch_sp(env); } -uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t result; - - shift &= 63; - result = (uint64_t)val << shift; - - env->cc_c = (result >> 32) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (uint64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (int64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = result ^ val; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - /* FPU helpers. */ uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val) { diff --git a/target-m68k/helper.h b/target-m68k/helper.h index 2697e32..aae01f9 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -3,9 +3,6 @@ DEF_HELPER_1(ff1, i32, i32) DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_2(divu, void, env, i32) DEF_HELPER_2(divs, void, env, i32) -DEF_HELPER_3(shl_cc, i32, env, i32, i32) -DEF_HELPER_3(shr_cc, i32, env, i32, i32) -DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 92e67eb..13ef117 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -562,7 +562,7 @@ static void gen_flush_flags(DisasContext *s) s->cc_op_synced = 1; } -static inline TCGv gen_extend(TCGv val, int opsize, int sign) +static TCGv gen_extend(TCGv val, int opsize, int sign) { TCGv tmp; @@ -2348,48 +2348,98 @@ DISAS_INSN(addx_mem) gen_store(s, opsize, addr_dest, QREG_CC_N); } -/* TODO: This could be implemented without helper functions. */ DISAS_INSN(shift_im) { - TCGv reg; - int tmp; - TCGv shift; + TCGv reg = DREG(insn, 0); + int count = (insn >> 9) & 7; + int logical = insn & 8; - set_cc_op(s, CC_OP_FLAGS); + if (count == 0) { + count = 8; + } - reg = DREG(insn, 0); - tmp = (insn >> 9) & 7; - if (tmp == 0) - tmp = 8; - shift = tcg_const_i32(tmp); - /* No need to flush flags becuse we know we will set C flag. */ if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, 31 - count); + tcg_gen_shli_i32(QREG_CC_N, reg, count); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); + if (logical) { + tcg_gen_shri_i32(QREG_CC_N, reg, count); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_sari_i32(QREG_CC_N, reg, count); } } + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); + + /* Note that ColdFire always clears V, while M68000 sets it for + a change in the sign bit. */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } else { + tcg_gen_movi_i32(QREG_CC_V, 0); + } + + tcg_gen_mov_i32(reg, QREG_CC_N); + set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(shift_reg) { - TCGv reg; - TCGv shift; + TCGv reg, s32; + TCGv_i64 t64, s64; + int logical = insn & 8; reg = DREG(insn, 0); - shift = DREG(insn, 9); + t64 = tcg_temp_new_i64(); + s64 = tcg_temp_new_i64(); + s32 = tcg_temp_new(); + + /* Note that m68k truncates the shift count modulo 64, not 32. + In addition, a 64-bit shift makes it easy to find "the last + bit shifted out", for the carry flag. */ + tcg_gen_andi_i32(s32, DREG(insn, 9), 63); + tcg_gen_extu_i32_i64(s64, s32); + + /* Non-arithmetic shift clears V. Use it as a source zero here. */ + tcg_gen_movi_i32(QREG_CC_V, 0); + if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shl_i64(t64, t64, s64); + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); + tcg_temp_free_i64(t64); + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shli_i64(t64, t64, 32); + if (logical) { + tcg_gen_shr_i64(t64, t64, s64); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_sar_i64(t64, t64, s64); } + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); + tcg_temp_free_i64(t64); + tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); } + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + + /* Note that X = C, but only if the shift count was non-zero. */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, + QREG_CC_C, QREG_CC_X); + tcg_temp_free(s32); + + /* Note that ColdFire always clears V (which we have done above), + while M68000 sets it for a change in the sign bit. */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } + + /* Write back the result. */ + tcg_gen_mov_i32(reg, QREG_CC_N); set_cc_op(s, CC_OP_FLAGS); }