From patchwork Sat Oct 29 21:10:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 9404169 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 38383606DC for ; Sat, 29 Oct 2016 21:11:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 298E428FDB for ; Sat, 29 Oct 2016 21:11:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E65A290C3; Sat, 29 Oct 2016 21:11:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91DE028FDB for ; Sat, 29 Oct 2016 21:11:28 +0000 (UTC) Received: from localhost ([::1]:55984 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c0auU-00033R-SG for patchwork-qemu-devel@patchwork.kernel.org; Sat, 29 Oct 2016 17:11:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c0atz-0002yq-Dc for qemu-devel@nongnu.org; Sat, 29 Oct 2016 17:10:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c0aty-0003IA-J5 for qemu-devel@nongnu.org; Sat, 29 Oct 2016 17:10:55 -0400 Received: from mx2.suse.de ([195.135.220.15]:39159) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c0att-0003F7-UB; Sat, 29 Oct 2016 17:10:50 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 20CBCAB9D; Sat, 29 Oct 2016 21:10:42 +0000 (UTC) From: Alexander Graf To: qemu-devel@nongnu.org Date: Sat, 29 Oct 2016 23:10:49 +0200 Message-Id: <1477775449-115472-2-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.8.5.6 In-Reply-To: <1477775449-115472-1-git-send-email-agraf@suse.de> References: <1477775449-115472-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [RFC 2/2] ARM: KVM: Enable in-kernel timers with user space gic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP When running with KVM enabled, you can choose between emulating the gic in kernel or user space. If the kernel supports in-kernel virtualization of the interrupt controller, it will default to that. If not, if will default to user space emulation. Unfortunately when running in user mode gic emulation, we miss out on timer events which are only available from kernel space. This patch leverages the new kernel/user space pending line synchronization for those timer events. Signed-off-by: Alexander Graf --- hw/arm/virt.c | 10 ++++++++++ target-arm/cpu.h | 3 +++ target-arm/kvm.c | 19 +++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 070bbf8..8ac81e3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -622,6 +622,16 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, } else if (type == 2) { create_v2m(vbi, pic); } + +#ifdef CONFIG_KVM + if (kvm_enabled() && !kvm_irqchip_in_kernel()) { + if (!kvm_check_extension(kvm_state, KVM_CAP_ARM_TIMER)) { + error_report("KVM with user space irqchip only works when the " + "host kernel supports KVM_CAP_ARM_TIMER"); + exit(1); + } + } +#endif } static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart, diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 19d967b..7686082 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -659,6 +659,9 @@ struct ARMCPU { ARMELChangeHook *el_change_hook; void *el_change_hook_opaque; + + /* Used to synchronize KVM and QEMU timer levels */ + uint8_t timer_irq_level; }; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/kvm.c b/target-arm/kvm.c index c00b94e..0d8b642 100644 --- a/target-arm/kvm.c +++ b/target-arm/kvm.c @@ -527,6 +527,25 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) { + ARMCPU *cpu; + + if (kvm_irqchip_in_kernel()) { + /* + * We only need to sync timer states with user-space interrupt + * controllers, so return early and save cycles if we don't. + */ + return MEMTXATTRS_UNSPECIFIED; + } + + cpu = ARM_CPU(cs); + + /* Synchronize our internal vtimer irq line with the kvm one */ + if (run->s.regs.timer_irq_level != cpu->timer_irq_level) { + qemu_set_irq(ARM_CPU(cs)->gt_timer_outputs[GTIMER_VIRT], + run->s.regs.timer_irq_level & KVM_ARM_TIMER_VTIMER); + cpu->timer_irq_level = run->s.regs.timer_irq_level; + } + return MEMTXATTRS_UNSPECIFIED; }