From patchwork Wed Nov 2 21:15:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 9409901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A7A8060721 for ; Wed, 2 Nov 2016 21:20:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 966F921050 for ; Wed, 2 Nov 2016 21:20:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8AFC728BA3; Wed, 2 Nov 2016 21:20:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3CBF52A5C9 for ; Wed, 2 Nov 2016 21:20:12 +0000 (UTC) Received: from localhost ([::1]:57794 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c22x9-00019d-Il for patchwork-qemu-devel@patchwork.kernel.org; Wed, 02 Nov 2016 17:20:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c22sw-0006bO-4s for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c22sr-0004Dn-PL for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:50 -0400 Received: from mout.kundenserver.de ([217.72.192.73]:54841) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c22sr-0004DT-Ct for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:45 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue102) with ESMTPSA (Nemesis) id 0MXYso-1cOXGY0V42-00WX6I; Wed, 02 Nov 2016 22:15:28 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 2 Nov 2016 22:15:19 +0100 Message-Id: <1478121319-31986-4-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478121319-31986-1-git-send-email-laurent@vivier.eu> References: <1478121319-31986-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:krIgc93/DkGn1DKR46gxz8ZNAURuifn37V8kkHg6QpmtZD5d1Z5 fpAGnIkqa80SIKdtLR8IWtof/ILCS1uNH5f9xwYc1qxRrbj/jIm+EQlpmCfV2XM3RS4WSC+ fJgQPA2oGkRCjEjdDFKVqO1M1sv4K+Yb+kPkr7C1y51eYWLdTnBGQoSgbxx03guLAHoikSF xXYeji8RIpSo0awmyWphQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:EfHOrwSNFQY=:2wMXozxn3S2uzdR6e7liR/ 9GzLdkdRXXwUYPDvoyadP/da9ktrBNOJTqbgqrN7lQbNUyeAzMuvuQW7s8OYJdeRm3mMQCNGd NcZAdMVrUySjEuV/5D8ZI2BA9GzkL0080US8VBmyfmKYaR6+8lRJanRHBH8reB/AdEwqiGNl0 J83JWVmmjRN5qdeNskMFouguSvk0VMw1ycSuFVCL2I8gM0nBQIJbqCG8oXFWnmiYqL4lVRxJA jOmidv47tQOzUKfrHPveXtfuRuBblI3bVR+c0gmv0sV//kALIfcgRleaLqqYL+M9n2OZ6uKPA zFaQu5frw4VikaUtor02860kT55Pv9bmEp/koBfnQ/CmpDkR9Qc8pyRDh9OrNi+VRUUhYk5up Dh7QyewEuL+XCs0cnSSqfGZh5JWpx/JEX29qhPNQTwADU+H92Ac/dcL+qZALHSz6h0K3Hy7c9 X0+EoLJIIwLtvszfuf3vWE7+505bLww3Ysr5jG7Oz6m34VaLzl4Pzpy8PUOWMbvlZW4Gkk9mc N+g/yeapgj+vFjs8j5TX05fznxd890gRkM1Jo8HMAk3opDjZrchhCaAdpCm+8+ciJYoveIEN4 qPtvo1CKCTaMSe/jL8ancJgOiWB+9NPX5DnmcxdXFPfWLpSRAoOIt1zwLZrfC+6PhCZJy7LSg i5PQZMbKTMn0+z5acVg4B6fRZ1Qsl/xQ0XyH0zaTXaN0QHoWnIxyqPwP8tUEDwHkQk1k= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.72.192.73 Subject: [Qemu-devel] [PATCH v2 3/3] target-m68k: add cas/cas2 ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Implement CAS using cmpxchg. Implement CAS2 using helper and either cmpxchg when the 32bit addresses are consecutive, or with parallel_cpus+cpu_loop_exit_atomic() otherwise. Suggested-by: Richard Henderson Signed-off-by: Laurent Vivier --- target-m68k/helper.h | 2 + target-m68k/op_helper.c | 133 ++++++++++++++++++++++++++++++++++++++++++++ target-m68k/translate.c | 143 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 278 insertions(+) diff --git a/target-m68k/helper.h b/target-m68k/helper.h index d863e55..17ec342 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -9,6 +9,8 @@ DEF_HELPER_4(divull, void, env, int, int, i32) DEF_HELPER_4(divsll, void, env, int, int, s32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) +DEF_HELPER_4(cas2w, void, env, i32, i32, i32) +DEF_HELPER_4(cas2l, void, env, i32, i32, i32) DEF_HELPER_2(f64_to_i32, f32, env, f64) DEF_HELPER_2(f64_to_f32, f32, env, f64) diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index a4bfa4e..ff27211 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -359,3 +359,136 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) env->dregs[regr] = rem; env->dregs[numr] = quot; } + +void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2) +{ + uint32_t Dc1 = extract32(regs, 9, 3); + uint32_t Dc2 = extract32(regs, 6, 3); + uint32_t Du1 = extract32(regs, 3, 3); + uint32_t Du2 = extract32(regs, 0, 3); + int16_t c1 = env->dregs[Dc1]; + int16_t c2 = env->dregs[Dc2]; + int16_t u1 = env->dregs[Du1]; + int16_t u2 = env->dregs[Du2]; + int16_t l1, l2; + uintptr_t ra = GETPC(); + + if (parallel_cpus) { + /* Tell the main loop we need to serialize this insn. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } else { + /* We're executing in a serial context -- no need to be atomic. */ +#ifdef CONFIG_USER_ONLY + int16_t *ha1 = g2h(a1); + int16_t *ha2 = g2h(a2); + l1 = ldsw_be_p(ha1); + l2 = ldsw_be_p(ha2); + if (l1 == c1 && l2 == c2) { + stw_be_p(ha1, u1); + stw_be_p(ha2, u2); + } +#else + int mmu_idx = cpu_mmu_index(env, 0); + TCGMemOpIdx oi = make_memop_idx(MO_BEUW, mmu_idx); + l1 = helper_be_ldsw_mmu(env, a1, oi, ra); + l2 = helper_be_ldsw_mmu(env, a2, oi, ra); + if (l1 == c1 && l2 == c2) { + helper_be_stw_mmu(env, a1, u1, oi, ra); + helper_be_stw_mmu(env, a2, u2, oi, ra); + } +#endif + } + + if (c1 != l1) { + env->cc_n = l1; + env->cc_v = c1; + } else { + env->cc_n = l2; + env->cc_v = c2; + } + env->cc_op = CC_OP_CMPL; + env->dregs[Dc1] = deposit32(env->dregs[Dc1], 0, 16, l1); + env->dregs[Dc2] = deposit32(env->dregs[Dc2], 0, 16, l2); +} + +void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2) +{ + uint32_t Dc1 = extract32(regs, 9, 3); + uint32_t Dc2 = extract32(regs, 6, 3); + uint32_t Du1 = extract32(regs, 3, 3); + uint32_t Du2 = extract32(regs, 0, 3); + uint32_t c1 = env->dregs[Dc1]; + uint32_t c2 = env->dregs[Dc2]; + uint32_t u1 = env->dregs[Du1]; + uint32_t u2 = env->dregs[Du2]; + uint32_t l1, l2; + uint64_t c, u, l; + uintptr_t ra = GETPC(); +#ifndef CONFIG_USER_ONLY + int mmu_idx = cpu_mmu_index(env, 0); + TCGMemOpIdx oi; +#endif + + if (parallel_cpus) { + /* We're executing in a parallel context -- must be atomic. */ + if ((a1 & 7) == 0 && a2 == a1 + 4) { + c = deposit64(c2, 32, 32, c1); + u = deposit64(u2, 32, 32, u1); +#ifdef CONFIG_USER_ONLY + uint64_t *ha1 = g2h(a1); + l = atomic_cmpxchg__nocheck(ha1, c, u); +#else + oi = make_memop_idx(MO_BEQ, mmu_idx); + l = helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); +#endif + l1 = l >> 32; + l2 = l; + } else if ((a2 & 7) == 0 && a1 == a2 + 4) { + c = deposit64(c1, 32, 32, c2); + u = deposit64(u1, 32, 32, u2); +#ifdef CONFIG_USER_ONLY + uint64_t *ha1 = g2h(a1); + l = atomic_cmpxchg__nocheck(ha1, c, u); +#else + oi = make_memop_idx(MO_BEQ, mmu_idx); + l = helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); +#endif + l2 = l >> 32; + l1 = l; + } else { + /* Tell the main loop we need to serialize this insn. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + } else { +#ifdef CONFIG_USER_ONLY + uint32_t *ha1 = g2h(a1); + uint32_t *ha2 = g2h(a2); + l1 = ldl_be_p(ha1); + l2 = ldl_be_p(ha2); + if (l1 == c1 && l2 == c2) { + stl_be_p(ha1, u1); + stl_be_p(ha2, u2); + } +#else + /* We're executing in a serial context -- no need to be atomic. */ + oi = make_memop_idx(MO_BEUL, mmu_idx); + l1 = helper_be_ldul_mmu(env, a1, oi, ra); + l2 = helper_be_ldul_mmu(env, a2, oi, ra); + if (l1 == c1 && l2 == c2) { + helper_be_stl_mmu(env, a1, u1, oi, ra); + helper_be_stl_mmu(env, a2, u2, oi, ra); + } +#endif + } + + if (c1 != l1) { + env->cc_n = l1; + env->cc_v = c1; + } else { + env->cc_n = l2; + env->cc_v = c2; + } + env->cc_op = CC_OP_CMPL; + env->dregs[Dc1] = l1; + env->dregs[Dc2] = l2; +} diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 93f1270..68cb8d4 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1880,6 +1880,146 @@ DISAS_INSN(arith_im) tcg_temp_free(dest); } +DISAS_INSN(cas) +{ + int opsize; + TCGv addr; + uint16_t ext; + TCGv load; + TCGv cmp; + TCGMemOp opc; + + switch ((insn >> 9) & 3) { + case 1: + opsize = OS_BYTE; + opc = MO_UB; + break; + case 2: + opsize = OS_WORD; + opc = MO_TEUW; + break; + case 3: + opsize = OS_LONG; + opc = MO_TEUL; + break; + default: + g_assert_not_reached(); + } + opc |= MO_ALIGN; + + ext = read_im16(env, s); + + /* cas Dc,Du, */ + + addr = gen_lea(env, s, insn, opsize); + if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); + return; + } + + cmp = gen_extend(DREG(ext, 0), opsize, 0); + + /* if == Dc then + * = Du + * Dc = (because == Dc) + * else + * Dc = + */ + + load = tcg_temp_new(); + tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6), + IS_USER(s), opc); + gen_partset_reg(opsize, DREG(ext, 0), load); + + gen_update_cc_cmp(s, load, cmp, opsize); + tcg_temp_free(load); +} + +DISAS_INSN(cas2w) +{ + uint16_t ext1, ext2; + TCGv addr1, addr2; + TCGv regs; + + /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ + + ext1 = read_im16(env, s); + + if (ext1 & 0x8000) { + /* Address Register */ + addr1 = AREG(ext1, 12); + } else { + /* Data Register */ + addr1 = DREG(ext1, 12); + } + + ext2 = read_im16(env, s); + if (ext2 & 0x8000) { + /* Address Register */ + addr2 = AREG(ext2, 12); + } else { + /* Data Register */ + addr2 = DREG(ext2, 12); + } + + /* if (R1) == Dc1 && (R2) == Dc2 then + * (R1) = Du1 + * (R2) = Du2 + * else + * Dc1 = (R1) + * Dc2 = (R2) + */ + + regs = tcg_const_i32(REG(ext2, 6) | + (REG(ext1, 6) << 3) | + (REG(ext2, 0) << 6) | + (REG(ext1, 0) << 9)); + gen_helper_cas2w(cpu_env, regs, addr1, addr2); + tcg_temp_free(regs); +} + +DISAS_INSN(cas2l) +{ + uint16_t ext1, ext2; + TCGv addr1, addr2, regs; + + /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ + + ext1 = read_im16(env, s); + + if (ext1 & 0x8000) { + /* Address Register */ + addr1 = AREG(ext1, 12); + } else { + /* Data Register */ + addr1 = DREG(ext1, 12); + } + + ext2 = read_im16(env, s); + if (ext2 & 0x8000) { + /* Address Register */ + addr2 = AREG(ext2, 12); + } else { + /* Data Register */ + addr2 = DREG(ext2, 12); + } + + /* if (R1) == Dc1 && (R2) == Dc2 then + * (R1) = Du1 + * (R2) = Du2 + * else + * Dc1 = (R1) + * Dc2 = (R2) + */ + + regs = tcg_const_i32(REG(ext2, 6) | + (REG(ext1, 6) << 3) | + (REG(ext2, 0) << 6) | + (REG(ext1, 0) << 9)); + gen_helper_cas2w(cpu_env, regs, addr1, addr2); + tcg_temp_free(regs); +} + DISAS_INSN(byterev) { TCGv reg; @@ -3885,6 +4025,9 @@ void register_m68k_insns (CPUM68KState *env) INSN(arith_im, 0680, fff8, CF_ISA_A); INSN(arith_im, 0c00, ff38, CF_ISA_A); INSN(arith_im, 0c00, ff00, M68000); + INSN(cas, 08c0, f9c0, CAS); + INSN(cas2w, 0cfc, ffff, CAS); + INSN(cas2l, 0efc, ffff, CAS); BASE(bitop_im, 0800, ffc0); BASE(bitop_im, 0840, ffc0); BASE(bitop_im, 0880, ffc0);