From patchwork Wed Nov 9 17:30:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 9419867 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 198AE6048E for ; Wed, 9 Nov 2016 17:31:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 03F9229399 for ; Wed, 9 Nov 2016 17:31:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EB2122939B; Wed, 9 Nov 2016 17:31:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 280D429399 for ; Wed, 9 Nov 2016 17:31:09 +0000 (UTC) Received: from localhost ([::1]:41517 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4WiK-0002Zu-Fi for patchwork-qemu-devel@patchwork.kernel.org; Wed, 09 Nov 2016 12:31:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4Whu-0002YP-Oa for qemu-devel@nongnu.org; Wed, 09 Nov 2016 12:30:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4Whm-0007X0-EW for qemu-devel@nongnu.org; Wed, 09 Nov 2016 12:30:42 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:65407) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c4Whm-0007Wa-4K for qemu-devel@nongnu.org; Wed, 09 Nov 2016 12:30:34 -0500 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue101 [212.227.15.183]) with ESMTPSA (Nemesis) id 0MY6Vs-1cHfrH0xAO-00UpT4; Wed, 09 Nov 2016 18:30:27 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 9 Nov 2016 18:30:03 +0100 Message-Id: <1478712603-18286-1-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 X-Provags-ID: V03:K0:W8s1zi67Q2e/Rn6t+FdwqLfzAnxjzIN8oOL5N+6LFI2AoqprkiP c9MkiyvWYUy/cxQqlg83E5e0e8gEQnyKpDjdWsMG5UyfnmpPCysdG6GwbC4BNsGnhxCw2hN 9HKs9bxoPWNI4qLs4uDS7bvZMiiMrdIQiQyzwd8af6CGpYOy/0fBBLZe2t3aJeVg6+YS8FF p/hhhGb9DQ5YdiB8ek9SQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:0YOF1YQGV7I=:6VP+0gbKYyDtuPh/M76Ks7 tDXVMkFDyJIc//uDFhKsttLY4kzch8EKOrIa3iP+ZYF33S2P97xdsA9524I+HV2mmggsu696I Ji3YrGRR7oOnW7fW0EpM13JHXCYL187XpZS2HAtyk08Cz0JrI9OyuKE9GwjnRGfKxN8QApMlS HC+LNBnNWRzfKiphtE1RnZPQEcMzCiDBqVdgq+01tFEefP8G8NLo51XE6IHvCKi+5rOY6P59r WMX6TtW7gCzDvLJd80PdMZwTJzBWTbWo6PEaYD/+FSsSH06xFpwMgfEWbglQ/tOlOWqUPCdSI eABFFZgsgJhMtAbFmcx8+vxIP31d7IVLcbOa9JR/hoyVhfs7akHoYmH6kYPeDHdtHNYAL7m1p 3+xgnIaschMnUOG5AsetWfa6X02GFBZ8Pbbwroy5GSKUsWIosIPF6zTyQFs+ASLXmYuRtahbT L3aU8cKWZaIYPDbwf/+QA1vAjRuj/oVcpl4aISU4W0LgP7/wtrwpegRwpNslTWy+FgVmS+ESX voT9AraSFH+pMjmBFabwFJpXBJ4Zqa180TQA2psyOvF/4svsyQEJa8tB/uzFBL9kPkBtuUtHt 6xJqfRlB6D1l5ISrARNIO+Ikh42Om2h+Y9I4aeexq0n1zZQfhxxY9VBhwTTrSeCVjYxoheQKV Po8qAKgUW+8lVHFc04ZAuJ3EFQqTkkcvlO5E4Ghj4LHxSPm931u9vjp7ZRP6us6V1buM= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.72.192.74 Subject: [Qemu-devel] [PATCH] target-m68k: add rol/ror/roxl/roxr instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 414 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 414 insertions(+) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index a17ff01..9686a24 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3080,6 +3080,413 @@ DISAS_INSN(shift_mem) set_cc_op(s, CC_OP_FLAGS); } +static void rotate(TCGv reg, TCGv shift, int left, int size) +{ + switch (size) { + case 8: + /* Replicate the 8-bit input so that a 32-bit rotate works. */ + tcg_gen_ext8u_i32(reg, reg); + tcg_gen_muli_i32(reg, reg, 0x01010101); + goto do_long; + case 16: + /* Replicate the 16-bit input so that a 32-bit rotate works. */ + tcg_gen_deposit_i32(reg, reg, reg, 16, 16); + goto do_long; + do_long: + default: + if (left) { + tcg_gen_rotl_i32(reg, reg, shift); + } else { + tcg_gen_rotr_i32(reg, reg, shift); + } + } + + /* compute flags */ + + switch (size) { + case 8: + tcg_gen_ext8s_i32(reg, reg); + break; + case 16: + tcg_gen_ext16s_i32(reg, reg); + break; + default: + break; + } + + /* QREG_CC_X is not affected */ + + tcg_gen_mov_i32(QREG_CC_N, reg); + tcg_gen_mov_i32(QREG_CC_Z, reg); + + if (left) { + tcg_gen_andi_i32(QREG_CC_C, reg, 1); + } else { + tcg_gen_shri_i32(QREG_CC_C, reg, 31); + } + + tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */ +} + +static void rotate_x_flags(TCGv reg, TCGv X, int size) +{ + switch (size) { + case 8: + tcg_gen_ext8s_i32(reg, reg); + break; + case 16: + tcg_gen_ext16s_i32(reg, reg); + break; + default: + break; + } + tcg_gen_mov_i32(QREG_CC_N, reg); + tcg_gen_mov_i32(QREG_CC_Z, reg); + tcg_gen_mov_i32(QREG_CC_X, X); + tcg_gen_mov_i32(QREG_CC_C, X); + tcg_gen_movi_i32(QREG_CC_V, 0); +} + +static TCGv rotate_x(TCGv dest, TCGv src, TCGv shift, int left, int size) +{ + TCGv X, t0, t1; + + X = tcg_temp_new(); + t0 = tcg_temp_new(); + if (left) { + /* create [src:X:..] */ + + tcg_gen_deposit_i32(t0, QREG_CC_X, src, 1, size); + tcg_gen_shli_i32(t0, t0, 31 - size); + + /* rotate */ + + tcg_gen_rotl_i32(t0, t0, shift); + + /* result is [src:..:src:X] */ + + tcg_gen_andi_i32(X, t0, 1); + tcg_gen_shri_i32(t0, t0, 1); + } else { + /* create [..:X:src] */ + + tcg_gen_deposit_i32(t0, src, QREG_CC_X, size, 1); + + /* rotate */ + + tcg_gen_rotr_i32(t0, t0, shift); + + /* result is value: [X:src:..:src] */ + + tcg_gen_shri_i32(X, t0, 31); + } + + /* extract result */ + + t1 = tcg_temp_new(); + tcg_gen_shri_i32(t1, t0, 31 - size); + tcg_gen_or_i32(dest, t0, t1); + tcg_temp_free(t1); + tcg_temp_free(t0); + + return X; +} + +static TCGv rotate32_x(TCGv dest, TCGv src, TCGv shift, int left) +{ + TCGv_i64 t0, shift64; + TCGv X, lo, hi; + + shift64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(shift64, shift); + + t0 = tcg_temp_new_i64(); + + X = tcg_temp_new(); + lo = tcg_temp_new(); + hi = tcg_temp_new(); + + if (left) { + /* create [src:X:..] */ + + tcg_gen_shli_i32(lo, QREG_CC_X, 31); + tcg_gen_concat_i32_i64(t0, lo, src); + + /* rotate */ + + tcg_gen_rotl_i64(t0, t0, shift64); + tcg_temp_free_i64(shift64); + + /* result is [src:..:src:X] */ + + tcg_gen_extr_i64_i32(lo, hi, t0); + tcg_gen_andi_i32(X, lo, 1); + + tcg_gen_shri_i32(lo, lo, 1); + } else { + /* create [..:X:src] */ + + tcg_gen_concat_i32_i64(t0, src, QREG_CC_X); + + tcg_gen_rotr_i64(t0, t0, shift64); + tcg_temp_free_i64(shift64); + + /* result is value: [X:src:..:src] */ + + tcg_gen_extr_i64_i32(lo, hi, t0); + + /* extract X */ + + tcg_gen_shri_i32(X, hi, 31); + + /* extract result */ + + tcg_gen_shli_i32(hi, hi, 1); + } + tcg_gen_or_i32(dest, lo, hi); + tcg_temp_free(hi); + tcg_temp_free(lo); + tcg_temp_free_i64(t0); + + return X; +} + +DISAS_INSN(rotate_im) +{ + TCGv shift; + int tmp; + int left = (insn & 0x100); + + tmp = (insn >> 9) & 7; + if (tmp == 0) { + tmp = 8; + } + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(DREG(insn, 0), shift, left, 32); + } else { + TCGv X = rotate32_x(DREG(insn, 0), DREG(insn, 0), shift, left); + rotate_x_flags(DREG(insn, 0), X, 32); + tcg_temp_free(X); + } + tcg_temp_free(shift); + + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate8_im) +{ + int left = (insn & 0x100); + TCGv reg; + TCGv shift; + int tmp; + + reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); + + tmp = (insn >> 9) & 7; + if (tmp == 0) { + tmp = 8; + } + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(reg, shift, left, 8); + } else { + TCGv X = rotate_x(reg, reg, shift, left, 8); + rotate_x_flags(reg, X, 8); + tcg_temp_free(X); + } + gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate16_im) +{ + int left = (insn & 0x100); + TCGv reg; + TCGv shift; + int tmp; + + reg = gen_extend(DREG(insn, 0), OS_WORD, 0); + tmp = (insn >> 9) & 7; + if (tmp == 0) { + tmp = 8; + } + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(reg, shift, left, 16); + } else { + TCGv X = rotate_x(reg, reg, shift, left, 16); + rotate_x_flags(reg, X, 8); + tcg_temp_free(X); + } + gen_partset_reg(OS_WORD, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate_reg) +{ + TCGv reg; + TCGv src; + TCGv t0, t1; + int left = (insn & 0x100); + + reg = DREG(insn, 0); + src = DREG(insn, 9); + t0 = tcg_temp_new(); + t1 = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(t0, src, 63); + tcg_gen_andi_i32(t1, src, 31); + rotate(reg, t1, left, 32); + /* if shift == 0, clear C */ + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + t0, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv X, zero, res; + /* shift in [0..63] */ + tcg_gen_andi_i32(t0, src, 63); + /* modulo 33 */ + tcg_gen_movi_i32(t1, 33); + tcg_gen_remu_i32(t1, t0, t1); + res = tcg_temp_new(); + X = rotate32_x(res, DREG(insn, 0), t1, left); + /* if shift == 0, register and X are not affected */ + zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, X, + t0, zero, + QREG_CC_X, X); + tcg_gen_movcond_i32(TCG_COND_EQ, DREG(insn, 0), + t0, zero, + DREG(insn, 0), res); + tcg_temp_free(res); + tcg_temp_free(zero); + rotate_x_flags(DREG(insn, 0), X, 32); + tcg_temp_free(X); + } + tcg_temp_free(t1); + tcg_temp_free(t0); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate8_reg) +{ + TCGv reg; + TCGv src; + TCGv t0, t1; + int left = (insn & 0x100); + + reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); + src = DREG(insn, 9); + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(t0, src, 63); + tcg_gen_andi_i32(t1, src, 7); + rotate(reg, t1, left, 8); + /* if shift == 0, clear C */ + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + t0, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv X, res, zero; + /* shift in [0..63] */ + tcg_gen_andi_i32(t0, src, 63); + /* modulo 9 */ + tcg_gen_movi_i32(t1, 9); + tcg_gen_remu_i32(t1, t0, t1); + res = tcg_temp_new(); + X = rotate_x(res, reg, t1, left, 8); + /* if shift == 0, register and X are not affected */ + zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, X, + t0, zero, + QREG_CC_X, X); + tcg_gen_movcond_i32(TCG_COND_EQ, reg, + t0, zero, + reg, res); + tcg_temp_free(res); + tcg_temp_free(zero); + rotate_x_flags(reg, X, 8); + tcg_temp_free(X); + } + tcg_temp_free(t1); + tcg_temp_free(t0); + gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate16_reg) +{ + TCGv reg; + TCGv src; + TCGv t0, t1; + int left = (insn & 0x100); + + reg = gen_extend(DREG(insn, 0), OS_WORD, 0); + src = DREG(insn, 9); + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(t0, src, 63); + tcg_gen_andi_i32(t1, src, 15); + rotate(reg, t1, left, 16); + /* if shift == 0, clear C */ + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + t0, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv X, res, zero; + /* shift in [0..63] */ + tcg_gen_andi_i32(t0, src, 63); + /* modulo 17 */ + t1 = tcg_const_i32(17); + tcg_gen_remu_i32(t1, t0, t1); + res = tcg_temp_new(); + X = rotate_x(res, reg, t1, left, 16); + /* if shift == 0, register and X are not affected */ + zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, X, + t0, zero, + QREG_CC_X, X); + tcg_gen_movcond_i32(TCG_COND_EQ, reg, + t0, zero, + reg, res); + tcg_temp_free(res); + tcg_temp_free(zero); + rotate_x_flags(reg, X, 16); + tcg_temp_free(X); + } + tcg_temp_free(t1); + tcg_temp_free(t0); + gen_partset_reg(OS_WORD, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate_mem) +{ + TCGv src; + TCGv addr; + TCGv shift; + int left = (insn & 0x100); + + SRC_EA(env, src, OS_WORD, 0, &addr); + + shift = tcg_const_i32(1); + if (insn & 8) { + rotate(src, shift, left, 16); + } else { + TCGv X = rotate_x(src, src, shift, left, 16); + rotate_x_flags(src, X, 16); + tcg_temp_free(X); + } + DEST_EA(env, insn, OS_WORD, src, &addr); + set_cc_op(s, CC_OP_FLAGS); +} + static void bitfield_param(uint16_t ext, TCGv *offset, TCGv *width, TCGv *mask) { TCGv tmp; @@ -4492,6 +4899,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(shift16_reg, e060, f0f0, M68000); INSN(shift_reg, e0a0, f0f0, M68000); INSN(shift_mem, e0c0, fcc0, M68000); + INSN(rotate_im, e090, f0f0, M68000); + INSN(rotate8_im, e010, f0f0, M68000); + INSN(rotate16_im, e050, f0f0, M68000); + INSN(rotate_reg, e0b0, f0f0, M68000); + INSN(rotate8_reg, e030, f0f0, M68000); + INSN(rotate16_reg, e070, f0f0, M68000); + INSN(rotate_mem, e4c0, fcc0, M68000); INSN(bitfield_mem,e8c0, f8c0, BITFIELD); INSN(bitfield_reg,e8c0, f8f8, BITFIELD); INSN(undef_fpu, f000, f000, CF_ISA_A);