| Message ID | 1479815165-31059-7-git-send-email-nikunj@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> writes: > stxsd: Store VSX Scalar Dword > stxssp: Store VSX Scalar SP > > Moreover, DQ-Form/DS-FORM instructions shares the same primary > opcode(0x3D), bits 29:31 are used to decode the instruction. Us e a > common routine to decode primary opcode(0x3D) - ds-form/dq-form > instructions. Realised that the below logic wast correct, should be something like this: static void gen_dform3D(DisasContext *ctx) { if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ switch (ctx->opcode & 0x7) { case 1: /* lxv */ if (ctx->insns_flags2 & PPC2_ISA300) { return gen_lxv(ctx); } break; case 5: /* stxv */ if (ctx->insns_flags2 & PPC2_ISA300) { return gen_stxv(ctx); } break; } } else { /* DS-FORM */ switch (ctx->opcode & 0x3) { case 0: /* lfdp */ if (ctx->insns_flags2 & PPC2_ISA205) { return gen_stfdp(ctx); } break; case 2: /* lxsd */ if (ctx->insns_flags2 & PPC2_ISA300) { return gen_stxsd(ctx); } break; case 3: /* lxssp */ if (ctx->insns_flags2 & PPC2_ISA300) { return gen_stxssp(ctx); } break; } } return gen_invalid(ctx); } Will correct it in next revision. > > Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> > --- > target-ppc/translate.c | 25 +++++++++++++++++++++++++ > target-ppc/translate/fp-ops.inc.c | 1 - > target-ppc/translate/vsx-impl.inc.c | 21 +++++++++++++++++++++ > 3 files changed, 46 insertions(+), 1 deletion(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index f280851..bce607b 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -6076,6 +6076,29 @@ static void gen_dform39(DisasContext *ctx) > return gen_invalid(ctx); > } > > +/* handles stfdp, stxsd, stxssp */ > +static void gen_dform3D(DisasContext *ctx) > +{ > + switch (ctx->opcode & 0x7) { > + case 0: /* lfdp */ > + if (ctx->insns_flags2 & PPC2_ISA205) { > + return gen_stfdp(ctx); > + } > + break; > + case 2: /* lxsd */ > + if (ctx->insns_flags2 & PPC2_ISA300) { > + return gen_stxsd(ctx); > + } > + break; > + case 3: /* lxssp */ > + if (ctx->insns_flags2 & PPC2_ISA300) { > + return gen_stxssp(ctx); > + } > + break; > + } > + return gen_invalid(ctx); > +} > +
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f280851..bce607b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6076,6 +6076,29 @@ static void gen_dform39(DisasContext *ctx) return gen_invalid(ctx); } +/* handles stfdp, stxsd, stxssp */ +static void gen_dform3D(DisasContext *ctx) +{ + switch (ctx->opcode & 0x7) { + case 0: /* lfdp */ + if (ctx->insns_flags2 & PPC2_ISA205) { + return gen_stfdp(ctx); + } + break; + case 2: /* lxsd */ + if (ctx->insns_flags2 & PPC2_ISA300) { + return gen_stxsd(ctx); + } + break; + case 3: /* lxssp */ + if (ctx->insns_flags2 & PPC2_ISA300) { + return gen_stxssp(ctx); + } + break; + } + return gen_invalid(ctx); +} + static opcode_t opcodes[] = { GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), @@ -6150,6 +6173,8 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), #endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), +/* handles stfdp, stxsd, stxssp */ +GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), diff --git a/target-ppc/translate/fp-ops.inc.c b/target-ppc/translate/fp-ops.inc.c index 3127fa0..3c6d05a 100644 --- a/target-ppc/translate/fp-ops.inc.c +++ b/target-ppc/translate/fp-ops.inc.c @@ -87,7 +87,6 @@ GEN_STXF(name, stop, 0x17, op | 0x00, type) GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT) GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) -GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index 1d7cd23..8ee44cf 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -332,6 +332,27 @@ static void gen_stxvb16x(DisasContext *ctx) tcg_temp_free(EA); } +#define VSX_STORE_SCALAR_DS(name, operation) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_imm_index(ctx, EA, 0x03); \ + gen_qemu_##operation(ctx, xth, EA); \ + /* NOTE: cpu_vsrl is undefined */ \ + tcg_temp_free(EA); \ +} + +VSX_LOAD_SCALAR_DS(stxsd, st64_i64) +VSX_LOAD_SCALAR_DS(stxssp, st32fs) + #define MV_VSRW(name, tcgop1, tcgop2, target, source) \ static void gen_##name(DisasContext *ctx) \ { \
stxsd: Store VSX Scalar Dword stxssp: Store VSX Scalar SP Moreover, DQ-Form/DS-FORM instructions shares the same primary opcode(0x3D), bits 29:31 are used to decode the instruction. Us e a common routine to decode primary opcode(0x3D) - ds-form/dq-form instructions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> --- target-ppc/translate.c | 25 +++++++++++++++++++++++++ target-ppc/translate/fp-ops.inc.c | 1 - target-ppc/translate/vsx-impl.inc.c | 21 +++++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-)