From patchwork Wed Dec 14 02:09:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 9473603 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 28FDF60823 for ; Wed, 14 Dec 2016 02:09:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BF622868E for ; Wed, 14 Dec 2016 02:09:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F2F64286E5; Wed, 14 Dec 2016 02:09:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 76D2B2868E for ; Wed, 14 Dec 2016 02:09:46 +0000 (UTC) Received: from localhost ([::1]:45009 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cGz0r-0002LQ-4z for patchwork-qemu-devel@patchwork.kernel.org; Tue, 13 Dec 2016 21:09:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cGz0P-0002DD-1p for qemu-devel@nongnu.org; Tue, 13 Dec 2016 21:09:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cGz0N-0001nd-IM for qemu-devel@nongnu.org; Tue, 13 Dec 2016 21:09:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:33036) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cGz0N-0001nR-CZ for qemu-devel@nongnu.org; Tue, 13 Dec 2016 21:09:15 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8D8BB4E4C4; Wed, 14 Dec 2016 02:09:14 +0000 (UTC) Received: from pxdev.xzpeter.org.com (dhcp-14-171.nay.redhat.com [10.66.14.171]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uBE298CA031686; Tue, 13 Dec 2016 21:09:12 -0500 From: Peter Xu To: qemu-devel@nongnu.org Date: Wed, 14 Dec 2016 10:09:04 +0800 Message-Id: <1481681345-32424-2-git-send-email-peterx@redhat.com> In-Reply-To: <1481681345-32424-1-git-send-email-peterx@redhat.com> References: <1481681345-32424-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Wed, 14 Dec 2016 02:09:14 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 1/2] intel_iommu: check validity for GAW bits in CE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, famz@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, alex.williamson@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently vt-d Context Entry (CE) only allows 39/48 bits address width. If guest software configured more than that, we complain and report. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 17 ++++++++++++++++- hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 5f3e351..517a2a3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -599,9 +599,19 @@ static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry *ce) return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW); } +/* Return 0 if failed to fetch valid aw */ static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce) { - return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9; + uint8_t aw = (ce->hi & VTD_CONTEXT_ENTRY_AW); + /* + * According to vt-d spec 10.4.2 bits 12:8, SAGAW only allows + * 39/48 bits. + */ + if (aw > VTD_CE_AW_48BIT) { + error_report("Context entry address width not supported (aw=%d)" , aw); + return 0; + } + return 30 + aw * 9; } static const uint64_t vtd_paging_entry_rsvd_field[] = { @@ -642,6 +652,11 @@ static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint64_t gpa, bool is_write, uint32_t ce_agaw = vtd_get_agaw_from_context_entry(ce); uint64_t access_right_check; + if (!ce_agaw) { + error_report("Illegal context entry AGAW"); + return -VTD_FR_CONTEXT_ENTRY_INV; + } + /* Check if @gpa is above 2^X-1, where X is the minimum of MGAW in CAP_REG * and AW in context-entry. */ diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 11abfa2..e808c67 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -406,6 +406,8 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CONTEXT_ENTRY_RSVD_LO (0xff0ULL | ~VTD_HAW_MASK) /* hi */ #define VTD_CONTEXT_ENTRY_AW 7ULL /* Adjusted guest-address-width */ +#define VTD_CE_AW_39BIT 1 +#define VTD_CE_AW_48BIT 2 #define VTD_CONTEXT_ENTRY_DID(val) (((val) >> 8) & VTD_DOMAIN_ID_MASK) #define VTD_CONTEXT_ENTRY_RSVD_HI 0xffffffffff000080ULL