From patchwork Fri Dec 30 08:55:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 9491921 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9D3D860417 for ; Fri, 30 Dec 2016 09:05:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7BD401FF1D for ; Fri, 30 Dec 2016 09:05:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6EF021FF65; Fri, 30 Dec 2016 09:05:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E1E631FF1D for ; Fri, 30 Dec 2016 09:05:44 +0000 (UTC) Received: from localhost ([::1]:38983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cMt8C-0006jv-1j for patchwork-qemu-devel@patchwork.kernel.org; Fri, 30 Dec 2016 04:05:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cMszS-000077-AS for qemu-devel@nongnu.org; Fri, 30 Dec 2016 03:56:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cMszP-0008NL-9W for qemu-devel@nongnu.org; Fri, 30 Dec 2016 03:56:42 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42940) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cMszP-0008N8-3e for qemu-devel@nongnu.org; Fri, 30 Dec 2016 03:56:39 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3570D619FA; Fri, 30 Dec 2016 08:56:38 +0000 (UTC) Received: from pxdev.xzpeter.org (vpn1-4-51.pek2.redhat.com [10.72.4.51]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uBU8u2Lw011949; Fri, 30 Dec 2016 03:56:33 -0500 From: Peter Xu To: qemu-devel@nongnu.org, kvm@vger.kernel.org Date: Fri, 30 Dec 2016 16:55:58 +0800 Message-Id: <1483088160-6714-7-git-send-email-peterx@redhat.com> In-Reply-To: <1483088160-6714-1-git-send-email-peterx@redhat.com> References: <1483088160-6714-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Fri, 30 Dec 2016 08:56:38 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH 6/8] intel-iommu: use atomic ops for irte index alloc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , peterx@redhat.com, agordeev@redhat.com, Jan Kiszka , Paolo Bonzini Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP To allow concurrent allocation of irte index. Meanwhile, move the IRTE setup debug line into the alloc since vtd_setup_msi() might not be the only one to dump this info in the future. Signed-off-by: Peter Xu --- lib/x86/intel-iommu.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/lib/x86/intel-iommu.c b/lib/x86/intel-iommu.c index 20b9240..a3ce678 100644 --- a/lib/x86/intel-iommu.c +++ b/lib/x86/intel-iommu.c @@ -13,6 +13,7 @@ #include "intel-iommu.h" #include "libcflat.h" #include "pci.h" +#include "atomic.h" /* * VT-d in QEMU currently only support 39 bits address width, which is @@ -239,9 +240,13 @@ void vtd_map_range(uint16_t sid, iova_t iova, phys_addr_t pa, size_t size) static uint16_t vtd_intr_index_alloc(void) { - static int index_ctr = 0; + static volatile int index_ctr = 0; + int ctr; + assert(index_ctr < 65535); - return index_ctr++; + ctr = atomic_inc_fetch(&index_ctr); + printf("INTR: alloc IRTE index %d\n", ctr); + return ctr; } static void vtd_setup_irte(struct pci_dev *dev, vtd_irte_t *irte, @@ -296,7 +301,6 @@ bool vtd_setup_msi(struct pci_dev *dev, int vector, int dest_id) assert(sizeof(vtd_msi_addr_t) == 8); assert(sizeof(vtd_msi_data_t) == 4); - printf("INTR: setup IRTE index %d\n", index); vtd_setup_irte(dev, irte + index, vector, dest_id); msi_addr.handle_15 = index >> 15 & 1;