From patchwork Fri Dec 30 15:21:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corey Minyard X-Patchwork-Id: 9492287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4AB0262AB9 for ; Fri, 30 Dec 2016 15:36:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3CD8A1FF8F for ; Fri, 30 Dec 2016 15:36:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 31C6C20564; Fri, 30 Dec 2016 15:36:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 790571FF8F for ; Fri, 30 Dec 2016 15:36:06 +0000 (UTC) Received: from localhost ([::1]:40370 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cMzDx-0005FN-C9 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 30 Dec 2016 10:36:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cMz0U-0002Mi-2L for qemu-devel@nongnu.org; Fri, 30 Dec 2016 10:22:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cMz0S-0000HM-Fh for qemu-devel@nongnu.org; Fri, 30 Dec 2016 10:22:10 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:35915) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cMz0S-0000GV-8W for qemu-devel@nongnu.org; Fri, 30 Dec 2016 10:22:08 -0500 Received: by mail-pg0-x241.google.com with SMTP id n5so22380839pgh.3 for ; Fri, 30 Dec 2016 07:22:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=0KdZtGqUUuO1fccHlbzIpnRjCLk+0m5kzYFMIynUJFU=; b=nWvLXuZO956F3EwOXYYSsxaLuCHFKAANS69GAR1a2S/otL9vS8YeINr38gRNyGq8HB bmo1B0ntIcZ9E/u6SPOsE9S6QY3e0avJz1U3gRvXrLm+3OvqGPKrOlsORnihmZIa72VQ suJtF8u9uvgZiYLSXcAZQUI8twAS6/pnyd9FI0BUFEHs7GOnv3mfZ3SOCLE5y/yuRDJT 1NOKbaRTZPscypGIS4PPQg8VxK5jq5ty8fbg1If4lEGQuxT0FaQv6WoK0bGe7gu/LBnW j0uwIg7lxb3MmF30H4NNBWTvotGKbhBoFrwv+PVxbqzKCmyisqkngyXGuy05K5+BGq4j e0kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=0KdZtGqUUuO1fccHlbzIpnRjCLk+0m5kzYFMIynUJFU=; b=HIH3KkxqehWSDIQnb3A1H51fWPjSIrP4v/vK3JgHAgBK/JtxTyfn2V1wL0gjiacHa1 CMuBCW+g+MBVmYXRZeEqMGCSii7pWvWW21evGVKYRg03ix2WifeYRYDfos2kXECmu1Xt RmE6R0HmYZpdTP3Axfs/gPYDZUtoPGfpfa9TbOjmXdv1I9gMza2YaGnzT1J3dE90Vdy+ ZAHEzhLKWGKAI6erQv4LLor7dJv+KfAJrRG/flEpifEdsMXODCZQOuTENwGk/ZCpw4u0 L+AIyO8AYxEaNidHEqc6gR42AnMhNMPrhwTXsAR/jdgL4vZs0Hzu/031nTuLchwHExoG TeWA== X-Gm-Message-State: AIkVDXKmo8SD+PnP5bZviXVTW/SLJditT00jmt1ndA2GSpvn6awlny/6gI8+eU2odbznmA== X-Received: by 10.98.9.149 with SMTP id 21mr44667699pfj.159.1483111327391; Fri, 30 Dec 2016 07:22:07 -0800 (PST) Received: from serve.minyard.net ([47.184.183.230]) by smtp.gmail.com with ESMTPSA id z62sm113511455pfz.19.2016.12.30.07.22.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Dec 2016 07:22:02 -0800 (PST) Received: from t430.minyard.net (unknown [IPv6:2001:470:b8f6:1b:3850:e313:ed7:8ae4]) by serve.minyard.net (Postfix) with ESMTPA id 28B6CA257; Fri, 30 Dec 2016 09:21:57 -0600 (CST) Received: by t430.minyard.net (Postfix, from userid 1000) id 0546D300090; Fri, 30 Dec 2016 09:21:52 -0600 (CST) From: minyard@acm.org To: qemu-devel@nongnu.org Date: Fri, 30 Dec 2016 09:21:37 -0600 Message-Id: <1483111310-24808-7-git-send-email-minyard@acm.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1483111310-24808-1-git-send-email-minyard@acm.org> References: <1483111310-24808-1-git-send-email-minyard@acm.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 06/19] i2c:pm_smbus: Add block transfer capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , minyard@acm.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Corey Minyard There was no block transfer code in pm_smbus.c, and it is needed for some devices. So add it. This adds both byte-by-byte block transfers and buffered block transfers. Signed-off-by: Corey Minyard --- hw/i2c/pm_smbus.c | 151 ++++++++++++++++++++++++++++++++++++++++++---- hw/i2c/smbus_ich9.c | 8 ++- include/hw/i2c/pm_smbus.h | 20 +++++- 3 files changed, 164 insertions(+), 15 deletions(-) diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index e7a8e92..686d411 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -30,6 +30,7 @@ #define SMBHSTDAT0 0x05 #define SMBHSTDAT1 0x06 #define SMBBLKDAT 0x07 +#define SMBAUXCTL 0x0d #define STS_HOST_BUSY (1 << 0) #define STS_INTR (1 << 1) @@ -58,6 +59,10 @@ #define PROT_BLOCK_DATA 5 #define PROT_I2C_BLOCK_READ 6 +#define AUX_PEC (1 << 0) +#define AUX_BLK (1 << 1) +#define AUX_MASK 0x3 + /*#define DEBUG*/ #ifdef DEBUG @@ -127,6 +132,51 @@ static void smb_transaction(PMSMBus *s) goto error; } break; + case PROT_BLOCK_DATA: + if (read) { + ret = smbus_read_block(bus, addr, cmd, s->smb_data, + sizeof(s->smb_data), !s->i2c_enable, + !s->i2c_enable); + if (ret < 0) { + goto error; + } + s->smb_index = 0; + s->op_done = false; + if (s->smb_auxctl & AUX_BLK) { + s->smb_stat |= STS_INTR; + } else { + s->smb_blkdata = s->smb_data[0]; + s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE; + } + s->smb_data0 = ret; + goto out; + } else { + if (s->smb_auxctl & AUX_BLK) { + if (s->smb_index != s->smb_data0) { + s->smb_index = 0; + goto error; + } + /* Data is already all written to the queue, just do + the operation. */ + s->smb_index = 0; + ret = smbus_write_block(bus, addr, cmd, s->smb_data, + s->smb_data0, !s->i2c_enable); + if (ret < 0) { + goto error; + } + s->op_done = true; + s->smb_stat |= STS_INTR; + s->smb_stat &= ~STS_HOST_BUSY; + } else { + s->op_done = false; + s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE; + s->smb_data[0] = s->smb_blkdata; + s->smb_index = 0; + ret = 0; + } + goto out; + } + break; default: goto error; } @@ -146,13 +196,13 @@ done: if (ret < 0) { goto error; } - s->smb_stat |= STS_BYTE_DONE | STS_INTR; + s->smb_stat |= STS_INTR; +out: return; error: s->smb_stat |= STS_DEV_ERR; return; - } static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, @@ -164,14 +214,61 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, " val=0x%02" PRIx64 "\n", addr, val); switch(addr) { case SMBHSTSTS: - s->smb_stat = (~(val & 0xff)) & s->smb_stat; - s->smb_index = 0; + s->smb_stat &= ~(val & ~STS_HOST_BUSY); + if (!s->op_done && !(s->smb_auxctl & AUX_BLK)) { + uint8_t read = s->smb_addr & 0x01; + + s->smb_index++; + if (!read && s->smb_index == s->smb_data0) { + uint8_t prot = (s->smb_ctl >> 2) & 0x07; + uint8_t cmd = s->smb_cmd; + uint8_t addr = s->smb_addr >> 1; + int ret; + + if (prot == PROT_I2C_BLOCK_READ) { + s->smb_stat |= STS_DEV_ERR; + goto out; + } + + ret = smbus_write_block(s->smbus, addr, cmd, s->smb_data, + s->smb_data0, !s->i2c_enable); + if (ret < 0) { + s->smb_stat |= STS_DEV_ERR; + goto out; + } + s->op_done = true; + s->smb_stat |= STS_INTR; + s->smb_stat &= ~STS_HOST_BUSY; + } else if (!read) { + s->smb_data[s->smb_index] = s->smb_blkdata; + s->smb_stat |= STS_BYTE_DONE; + } else if (s->smb_ctl & CTL_LAST_BYTE) { + s->op_done = true; + s->smb_blkdata = s->smb_data[s->smb_index]; + s->smb_index = 0; + s->smb_stat |= STS_INTR; + s->smb_stat &= ~STS_HOST_BUSY; + } else { + s->smb_blkdata = s->smb_data[s->smb_index]; + s->smb_stat |= STS_BYTE_DONE; + } + } break; case SMBHSTCNT: - s->smb_ctl = val; - if (s->smb_ctl & CTL_START) { + s->smb_ctl = val & ~CTL_START; /* CTL_START always reads 0 */ + if (val & CTL_START) { + if (!s->op_done) { + s->smb_index = 0; + s->op_done = true; + } smb_transaction(s); } + if (s->smb_ctl & CTL_KILL) { + s->op_done = true; + s->smb_index = 0; + s->smb_stat |= STS_FAILED; + s->smb_stat &= ~STS_HOST_BUSY; + } break; case SMBHSTCMD: s->smb_cmd = val; @@ -186,13 +283,24 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, s->smb_data1 = val; break; case SMBBLKDAT: - s->smb_data[s->smb_index++] = val; - if (s->smb_index > 31) + if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) { s->smb_index = 0; + } + if (s->smb_auxctl & AUX_BLK) { + s->smb_data[s->smb_index++] = val; + } else { + s->smb_blkdata = val; + } + break; + case SMBAUXCTL: + s->smb_auxctl = val & AUX_MASK; break; default: break; } + + out: + return; } static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) @@ -205,7 +313,6 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) val = s->smb_stat; break; case SMBHSTCNT: - s->smb_index = 0; val = s->smb_ctl & CTL_RETURN_MASK; break; case SMBHSTCMD: @@ -221,9 +328,22 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) val = s->smb_data1; break; case SMBBLKDAT: - val = s->smb_data[s->smb_index++]; - if (s->smb_index > 31) + if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) { s->smb_index = 0; + } + if (s->smb_auxctl & AUX_BLK) { + val = s->smb_data[s->smb_index++]; + if (!s->op_done && s->smb_index == s->smb_data0) { + s->op_done = true; + s->smb_index = 0; + s->smb_stat &= ~STS_HOST_BUSY; + } + } else { + val = s->smb_blkdata; + } + break; + case SMBAUXCTL: + val = s->smb_auxctl; break; default: val = 0; @@ -235,6 +355,13 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) return val; } +static void pm_smbus_reset(PMSMBus *s) +{ + s->op_done = true; + s->smb_index = 0; + s->smb_stat = 0; +} + static const MemoryRegionOps pm_smbus_ops = { .read = smb_ioport_readb, .write = smb_ioport_writeb, @@ -245,6 +372,8 @@ static const MemoryRegionOps pm_smbus_ops = { void pm_smbus_init(DeviceState *parent, PMSMBus *smb) { + smb->op_done = true; + smb->reset = pm_smbus_reset; smb->smbus = i2c_init_bus(parent, "i2c"); memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb, "pm-smbus", 64); diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 48fab22..686ed09 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -62,12 +62,16 @@ static void ich9_smbus_write_config(PCIDevice *d, uint32_t address, pci_default_write_config(d, address, val, len); if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) { uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC]; - if ((hostc & ICH9_SMB_HOSTC_HST_EN) && - !(hostc & ICH9_SMB_HOSTC_I2C_EN)) { + if (hostc & ICH9_SMB_HOSTC_HST_EN) { memory_region_set_enabled(&s->smb.io, true); } else { memory_region_set_enabled(&s->smb.io, false); } + s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0; + if (hostc & ICH9_SMB_HOSTC_SSRESET) { + s->smb.reset(&s->smb); + s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET; + } } } diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h index 2a837af..99d5489 100644 --- a/include/hw/i2c/pm_smbus.h +++ b/include/hw/i2c/pm_smbus.h @@ -1,6 +1,8 @@ #ifndef PM_SMBUS_H #define PM_SMBUS_H +#define PM_SMBUS_MAX_MSG_SIZE 32 + typedef struct PMSMBus { I2CBus *smbus; MemoryRegion io; @@ -11,8 +13,22 @@ typedef struct PMSMBus { uint8_t smb_addr; uint8_t smb_data0; uint8_t smb_data1; - uint8_t smb_data[32]; - uint8_t smb_index; + uint8_t smb_data[PM_SMBUS_MAX_MSG_SIZE]; + uint8_t smb_blkdata; + uint8_t smb_auxctl; + uint32_t smb_index; + + /* Set by pm_smbus.c */ + void (*reset)(struct PMSMBus *s); + + /* Set by the user. */ + bool i2c_enable; + + /* Internally used by pm_smbus. */ + + /* Set on block transfers after the last byte has been read, so the + INTR bit can be set at the right time. */ + bool op_done; } PMSMBus; void pm_smbus_init(DeviceState *parent, PMSMBus *smb);