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[78.51.226.184]) by smtp.gmail.com with ESMTPSA id l67sm8048248wmf.1.2017.01.18.14.39.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Jan 2017 14:39:12 -0800 (PST) From: Artyom Tarasenko To: peter.maydell@linaro.org Date: Wed, 18 Jan 2017 23:38:17 +0100 Message-Id: <1484779123-18968-5-git-send-email-atar4qemu@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1484779123-18968-1-git-send-email-atar4qemu@gmail.com> References: <1484779123-18968-1-git-send-email-atar4qemu@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, qemu-devel@nongnu.org, Artyom Tarasenko , rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Artyom Tarasenko --- target/sparc/cpu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 10c9ac6..4c4c159 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -304,19 +304,36 @@ enum { #define TTE_W_OK_BIT (1ULL << 1) #define TTE_GLOBAL_BIT (1ULL << 0) +#define TTE_NFO_BIT_UA2005 (1ULL << 62) +#define TTE_USED_BIT_UA2005 (1ULL << 47) +#define TTE_LOCKED_BIT_UA2005 (1ULL << 61) +#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) +#define TTE_PRIV_BIT_UA2005 (1ULL << 8) +#define TTE_W_OK_BIT_UA2005 (1ULL << 6) + #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) +#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) + +#define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) +#define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) +#define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) +#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) +#define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) +#define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) + #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) +#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */