From patchwork Thu Feb 16 00:27:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 9576057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F21F9600C5 for ; Thu, 16 Feb 2017 00:33:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E440F2857B for ; Thu, 16 Feb 2017 00:33:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D911F2857F; Thu, 16 Feb 2017 00:33:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 83E982857B for ; Thu, 16 Feb 2017 00:33:16 +0000 (UTC) Received: from localhost ([::1]:43622 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceA0Z-0004Ff-Ic for patchwork-qemu-devel@patchwork.kernel.org; Wed, 15 Feb 2017 19:33:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46536) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ce9vZ-0008BM-Ic for qemu-devel@nongnu.org; Wed, 15 Feb 2017 19:28:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ce9vY-0001J9-Lu for qemu-devel@nongnu.org; Wed, 15 Feb 2017 19:28:05 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:20181) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ce9vY-0001J1-FF for qemu-devel@nongnu.org; Wed, 15 Feb 2017 19:28:04 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 8FFFB4EBA4EF5; Thu, 16 Feb 2017 00:27:58 +0000 (GMT) Received: from localhost.localdomain (192.168.161.53) by hhmail02.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 16 Feb 2017 00:28:02 +0000 From: Yongbok Kim To: Date: Thu, 16 Feb 2017 00:27:26 +0000 Message-ID: <1487204850-16448-5-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1487204850-16448-1-git-send-email-yongbok.kim@imgtec.com> References: <1487204850-16448-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.161.53] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH v5 4/8] target-mips: Provide function to test if a CPU supports an ISA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Burton , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Paul Burton Provide a new cpu_supports_isa function which allows callers to determine whether a CPU supports one of the ISA_ flags, by testing whether the associated struct mips_def_t sets the ISA flags in its insn_flags field. An example use of this is to allow boards which generate bootloader code to determine the properties of the CPU that will be used, for example whether the CPU is 64 bit or which architecture revision it implements. Signed-off-by: Paul Burton Reviewed-by: Leon Alrae Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Yongbok Kim --- target/mips/cpu.h | 1 + target/mips/translate.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e1c78f5..4a4747a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -815,6 +815,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) bool cpu_supports_cps_smp(const char *cpu_model); +bool cpu_supports_isa(const char *cpu_model, unsigned int isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* TODO QOM'ify CPU reset and remove */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 7f8ecf4..8b4a072 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20233,6 +20233,16 @@ bool cpu_supports_cps_smp(const char *cpu_model) return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } +bool cpu_supports_isa(const char *cpu_model, unsigned int isa) +{ + const mips_def_t *def = cpu_mips_find_by_name(cpu_model); + if (!def) { + return false; + } + + return (def->insn_flags & isa) != 0; +} + void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));