From patchwork Wed Apr 19 17:41:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lindsay X-Patchwork-Id: 9688561 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 23B8E602DC for ; Wed, 19 Apr 2017 17:51:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A57B28354 for ; Wed, 19 Apr 2017 17:51:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0F24C2841F; Wed, 19 Apr 2017 17:51:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91CE628354 for ; Wed, 19 Apr 2017 17:51:16 +0000 (UTC) Received: from localhost ([::1]:49659 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tl5-0006pc-RZ for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Apr 2017 13:51:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tcA-0008Jq-1T for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tc7-0004RK-J6 for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:02 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37842) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc4-0004P3-Np; Wed, 19 Apr 2017 13:41:56 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DD146610DB; Wed, 19 Apr 2017 17:41:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623715; bh=OTbX9A7wytE4wdwL05+NR5tWAO1elhLdDEHA/I2z1y4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ogwq6Rwm5mDk3OujlwrieV4/DkAgGKOyGVumWPL0FUC/ipvu3XJ80ehthDaXySP3C WR9mS/9WDAddk+AZhhsEIPJi3ID7Uj5VZK0cW6rBxtKHpf2ktVPxLzbYI/SY+fA5QF 3t++b1ThfpMoUT7TB5rb60XlHT4R03ih9tJGb5SE= Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D2C9D610D4; Wed, 19 Apr 2017 17:41:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623715; bh=OTbX9A7wytE4wdwL05+NR5tWAO1elhLdDEHA/I2z1y4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ogwq6Rwm5mDk3OujlwrieV4/DkAgGKOyGVumWPL0FUC/ipvu3XJ80ehthDaXySP3C WR9mS/9WDAddk+AZhhsEIPJi3ID7Uj5VZK0cW6rBxtKHpf2ktVPxLzbYI/SY+fA5QF 3t++b1ThfpMoUT7TB5rb60XlHT4R03ih9tJGb5SE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D2C9D610D4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:20 -0400 Message-Id: <1492623684-25799-10-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 4 ++++ target/arm/cpu.h | 10 ++++++++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 44c965c..d61ea12 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -788,6 +788,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (!cpu->has_pmu) { cpu->has_pmu = false; unset_feature(env, ARM_FEATURE_PMU); + } else { + uint64_t pmceid = get_pmceid(&cpu->env); + cpu->pmceid0 = pmceid & 0xffffffff; + cpu->pmceid1 = (pmceid >> 32) & 0xffffffff; } if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f3524f6..57ca684 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -780,6 +780,16 @@ void pmccntr_sync(CPUARMState *env); */ void pmu_sync(CPUARMState *env); +/* + * get_pmceid + * @env: CPUARMState + * + * Return the PMCEID[01] register values corresponding to the counters which + * are supported given the current configuration (0 is low 32, 1 is high 32 + * bits) + */ +uint64_t get_pmceid(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d07f72..a0ae201 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -891,6 +891,43 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ #define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) - 1)) +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 10 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01]) */ + bool (*supported)(CPUARMState *); + /* Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function */ + uint64_t (*get_count)(CPUARMState *); +} pm_event; + +#define SUPPORTED_EVENT_SENTINEL UINT16_MAX +static const pm_event pm_events[] = { + { .number = SUPPORTED_EVENT_SENTINEL } +}; +static uint16_t supported_event_map[0x3f]; + +/* + * Called upon initialization to build PMCEID0 (low 32 bits) and PMCEID1 (high + * 32). We also use it to build a map of ARM event numbers to indices in + * our pm_events array. + */ +uint64_t get_pmceid(CPUARMState *env) +{ + uint64_t pmceid = 0; + unsigned int i = 0; + while (pm_events[i].number != SUPPORTED_EVENT_SENTINEL) { + const pm_event *cnt = &pm_events[i]; + if (cnt->number < 0x3f && cnt->supported(env)) { + pmceid |= (1 << cnt->number); + supported_event_map[cnt->number] = i; + } else { + supported_event_map[cnt->number] = SUPPORTED_EVENT_SENTINEL; + } + i++; + } + return pmceid; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) {