From patchwork Tue Apr 25 09:49:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 9697803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 47A8460224 for ; Tue, 25 Apr 2017 09:50:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3D39B212BE for ; Tue, 25 Apr 2017 09:50:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 31FF4284E5; Tue, 25 Apr 2017 09:50:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91127212BE for ; Tue, 25 Apr 2017 09:50:15 +0000 (UTC) Received: from localhost ([::1]:48049 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2x6s-0004Tr-Cp for patchwork-qemu-devel@patchwork.kernel.org; Tue, 25 Apr 2017 05:50:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39355) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2x6K-0004Tj-Ll for qemu-devel@nongnu.org; Tue, 25 Apr 2017 05:49:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2x6F-0003r4-ON for qemu-devel@nongnu.org; Tue, 25 Apr 2017 05:49:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39724) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d2x6F-0003qv-FT for qemu-devel@nongnu.org; Tue, 25 Apr 2017 05:49:35 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3F30B7F3E1; Tue, 25 Apr 2017 09:49:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 3F30B7F3E1 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=peterx@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 3F30B7F3E1 Received: from pxdev.xzpeter.org.com (ovpn-8-91.pek2.redhat.com [10.72.8.91]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1E485903E4; Tue, 25 Apr 2017 09:49:23 +0000 (UTC) From: Peter Xu To: qemu-devel@nongnu.org Date: Tue, 25 Apr 2017 17:49:13 +0800 Message-Id: <1493113753-30025-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 25 Apr 2017 09:49:34 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH] pc: add 2.10 machine type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , peterx@redhat.com, Marcel Apfelbaum , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP CC: "Michael S. Tsirkin" CC: Paolo Bonzini CC: Richard Henderson CC: Eduardo Habkost Signed-off-by: Peter Xu Reviewed-by: Eduardo Habkost --- hw/i386/pc_piix.c | 15 ++++++++++++--- hw/i386/pc_q35.c | 13 +++++++++++-- include/hw/i386/pc.h | 3 +++ 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 9f102aa..8fb6553 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -437,21 +437,30 @@ static void pc_i440fx_machine_options(MachineClass *m) m->default_display = "std"; } -static void pc_i440fx_2_9_machine_options(MachineClass *m) +static void pc_i440fx_2_10_machine_options(MachineClass *m) { pc_i440fx_machine_options(m); m->alias = "pc"; m->is_default = 1; } +DEFINE_I440FX_MACHINE(v2_10, "pc-i440fx-2.10", NULL, + pc_i440fx_2_10_machine_options); + +static void pc_i440fx_2_9_machine_options(MachineClass *m) +{ + pc_i440fx_2_10_machine_options(m); + m->is_default = 0; + m->alias = NULL; + SET_MACHINE_COMPAT(m, PC_COMPAT_2_9); +} + DEFINE_I440FX_MACHINE(v2_9, "pc-i440fx-2.9", NULL, pc_i440fx_2_9_machine_options); static void pc_i440fx_2_8_machine_options(MachineClass *m) { pc_i440fx_2_9_machine_options(m); - m->is_default = 0; - m->alias = NULL; SET_MACHINE_COMPAT(m, PC_COMPAT_2_8); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index dd792a8..f07ebec 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -301,19 +301,28 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus = 288; } -static void pc_q35_2_9_machine_options(MachineClass *m) +static void pc_q35_2_10_machine_options(MachineClass *m) { pc_q35_machine_options(m); m->alias = "q35"; } +DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, + pc_q35_2_10_machine_options); + +static void pc_q35_2_9_machine_options(MachineClass *m) +{ + pc_q35_2_10_machine_options(m); + m->alias = NULL; + SET_MACHINE_COMPAT(m, PC_COMPAT_2_9); +} + DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, pc_q35_2_9_machine_options); static void pc_q35_2_8_machine_options(MachineClass *m) { pc_q35_2_9_machine_options(m); - m->alias = NULL; SET_MACHINE_COMPAT(m, PC_COMPAT_2_8); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f278b3a..7546d01 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -373,6 +373,9 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); +#define PC_COMPAT_2_9 \ + HW_COMPAT_2_9 \ + #define PC_COMPAT_2_8 \ HW_COMPAT_2_8 \ {\