From patchwork Wed Apr 26 10:06:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Yi L" X-Patchwork-Id: 9701069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B6FF460245 for ; Wed, 26 Apr 2017 10:41:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A117328459 for ; Wed, 26 Apr 2017 10:41:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95D94285EF; Wed, 26 Apr 2017 10:41:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 15CFC28459 for ; Wed, 26 Apr 2017 10:41:43 +0000 (UTC) Received: from localhost ([::1]:54138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d3KOF-0000t1-3c for patchwork-qemu-devel@patchwork.kernel.org; Wed, 26 Apr 2017 06:41:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d3K89-0003ZT-Vt for qemu-devel@nongnu.org; Wed, 26 Apr 2017 06:25:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d3K88-0002lW-W5 for qemu-devel@nongnu.org; Wed, 26 Apr 2017 06:25:06 -0400 Received: from mga09.intel.com ([134.134.136.24]:7861) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d3K88-0002j3-Hs for qemu-devel@nongnu.org; Wed, 26 Apr 2017 06:25:04 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Apr 2017 03:25:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,254,1488873600"; d="scan'208";a="79066635" Received: from sky-dev.bj.intel.com ([10.238.145.47]) by orsmga002.jf.intel.com with ESMTP; 26 Apr 2017 03:25:01 -0700 From: "Liu, Yi L" To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Date: Wed, 26 Apr 2017 18:06:50 +0800 Message-Id: <1493201210-14357-21-git-send-email-yi.l.liu@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1493201210-14357-1-git-send-email-yi.l.liu@linux.intel.com> References: <1493201210-14357-1-git-send-email-yi.l.liu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 Subject: [Qemu-devel] [RFC PATCH 20/20] intel_iommu: propagate Ext-Device-TLB invalidate to host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tianyu.lan@intel.com, "Liu, Yi L" , kevin.tian@intel.com, yi.l.liu@intel.com, ashok.raj@intel.com, kvm@vger.kernel.org, jean-philippe.brucker@arm.com, jasowang@redhat.com, iommu@lists.linux-foundation.org, jacob.jun.pan@intel.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP For Extended-Device-TLB invalidation, intel_iommu emulator needs to check all the assigned device and find the affected device. Replace the guest SID with the host SID in the invalidate descriptor and pass the request to host. Host may just submit the request to corresponding invalidation queue in pIOMMU. In future maybe PASID needs to be replaced. Signed-off-by: Liu, Yi L --- hw/i386/intel_iommu.c | 43 ++++++++++++++++++++++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 7 +++++++ 2 files changed, 50 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c5e9170..4370790 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2012,6 +2012,13 @@ static void vtd_tlb_inv_notify_hook(VTDNotifierIterator *iter, } else { return; } + case VTD_INV_DESC_EXT_DIOTLB: + if (iter->sid != *tlb_hook_info->sid) { + return; + } + tlb_hook_info->inv_desc->lo &= ~VTD_INV_DESC_EXT_DIOTLB_SID_MASK; + tlb_hook_info->inv_desc->lo |= (iter->host_sid << 16); + break; default: return; } @@ -2147,6 +2154,34 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s, return true; } +static bool vtd_process_ext_device_iotlb(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint32_t pasid; + uint16_t sid; + VTDIOTLBInvHookInfo tlb_hook_info; + + if ((inv_desc->lo & VTD_INV_DESC_EXT_DIOTLB_RSVD_LO) || + (inv_desc->hi & VTD_INV_DESC_EXT_DIOTLB_RSVD_HI)) { + VTD_DPRINTF(GENERAL, "error: non-zero reserved field in" + " Device ExIOTLB desc, hi 0x%"PRIx64 " lo 0x%"PRIx64, + inv_desc->hi, inv_desc->lo); + return false; + } + + pasid = VTD_INV_DESC_EXT_DIOTLB_PASID(inv_desc->lo); + sid = VTD_INV_DESC_EXT_DIOTLB_SID(inv_desc->lo); + + tlb_hook_info.did = NULL; + tlb_hook_info.sid = &sid; + tlb_hook_info.pasid = &pasid; + tlb_hook_info.inv_desc = inv_desc; + vtd_tlb_inv_passdown_notify(s, + &tlb_hook_info, + vtd_tlb_inv_notify_hook); + return true; +} + static bool vtd_process_inv_desc(IntelIOMMUState *s) { VTDInvDesc inv_desc; @@ -2190,6 +2225,14 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; + case VTD_INV_DESC_EXT_DIOTLB: + trace_vtd_inv_desc("device-extended-iotlb", + inv_desc.hi, inv_desc.lo); + if (!vtd_process_ext_device_iotlb(s, &inv_desc)) { + return false; + } + break; + case VTD_INV_DESC_WAIT: trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo); if (!vtd_process_wait_desc(s, &inv_desc)) { diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index a6b9350..3cb2361 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -343,6 +343,7 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */ #define VTD_INV_DESC_EXT_IOTLB 0x6 /* Ext-IOTLB Invalidate Desc */ #define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc */ +#define VTD_INV_DESC_EXT_DIOTLB 0x8 /* Ext-DIOTLB Invalidate Desc */ #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */ /* Masks for Invalidation Wait Descriptor*/ @@ -407,6 +408,12 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PASIDC_ALL_ALL (0ULL << 4) #define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4) +#define VTD_INV_DESC_EXT_DIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_EXT_DIOTLB_SID(val) (((val) >> 16) & 0xffff) +#define VTD_INV_DESC_EXT_DIOTLB_RSVD_LO 0xe00ULL +#define VTD_INV_DESC_EXT_DIOTLB_RSVD_HI 0x7feULL +#define VTD_INV_DESC_EXT_DIOTLB_SID_MASK 0xFFFF0000ULL + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id;