From patchwork Wed Apr 26 10:11:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Liu X-Patchwork-Id: 9701043 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F3F8C603F6 for ; Wed, 26 Apr 2017 10:32:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF92D2849F for ; Wed, 26 Apr 2017 10:32:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C46BD285EF; Wed, 26 Apr 2017 10:32:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ED2E0285F4 for ; Wed, 26 Apr 2017 10:32:48 +0000 (UTC) Received: from localhost ([::1]:54076 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d3KFc-00019q-60 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 26 Apr 2017 06:32:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d3KBN-0006t6-35 for qemu-devel@nongnu.org; Wed, 26 Apr 2017 06:28:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d3KBL-0004LR-FK for qemu-devel@nongnu.org; Wed, 26 Apr 2017 06:28:24 -0400 Received: from mga03.intel.com ([134.134.136.65]:33549) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d3KBL-0004JF-2P for qemu-devel@nongnu.org; Wed, 26 Apr 2017 06:28:23 -0400 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Apr 2017 03:28:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,254,1488873600"; d="scan'208";a="80991964" Received: from sky-dev.bj.intel.com ([10.238.145.47]) by orsmga004.jf.intel.com with ESMTP; 26 Apr 2017 03:28:19 -0700 From: "Liu, Yi L" To: kvm@vger.kernel.org, iommu@lists.linux-foundation.org, alex.williamson@redhat.com, peterx@redhat.com Date: Wed, 26 Apr 2017 18:11:58 +0800 Message-Id: <1493201525-14418-2-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1493201525-14418-1-git-send-email-yi.l.liu@intel.com> References: <1493201525-14418-1-git-send-email-yi.l.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [RFC PATCH 1/8] iommu: Introduce bind_pasid_table API function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tianyu.lan@intel.com, "Liu, Yi L" , kevin.tian@intel.com, yi.l.liu@intel.com, ashok.raj@intel.com, jean-philippe.brucker@arm.com, jasowang@redhat.com, qemu-devel@nongnu.org, Jacob Pan , jacob.jun.pan@intel.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Jacob Pan Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use case in the guest: https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html As part of the proposed architecture, when a SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) and performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID. A new IOMMU driver interface is therefore needed to perform tasks as follows: * Enable nested translation and appropriate translation type * Assign guest PASID table pointer (in GPA) and size to host IOMMU This patch introduces new functions called iommu_(un)bind_pasid_table() to IOMMU APIs. Architecture specific IOMMU function can be added later to perform the specific steps for binding pasid table of assigned devices. This patch also adds model definition in iommu.h. It would be used to check if the bind request is from a compatible entity. e.g. a bind request from an intel_iommu emulator may not be supported by an ARM SMMU driver. Signed-off-by: Jacob Pan Signed-off-by: Liu, Yi L --- drivers/iommu/iommu.c | 19 +++++++++++++++++++ include/linux/iommu.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index dbe7f65..f2da636 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1134,6 +1134,25 @@ int iommu_attach_device(struct iommu_domain *domain, struct device *dev) } EXPORT_SYMBOL_GPL(iommu_attach_device); +int iommu_bind_pasid_table(struct iommu_domain *domain, struct device *dev, + struct pasid_table_info *pasidt_binfo) +{ + if (unlikely(!domain->ops->bind_pasid_table)) + return -EINVAL; + + return domain->ops->bind_pasid_table(domain, dev, pasidt_binfo); +} +EXPORT_SYMBOL_GPL(iommu_bind_pasid_table); + +int iommu_unbind_pasid_table(struct iommu_domain *domain, struct device *dev) +{ + if (unlikely(!domain->ops->unbind_pasid_table)) + return -EINVAL; + + return domain->ops->unbind_pasid_table(domain, dev); +} +EXPORT_SYMBOL_GPL(iommu_unbind_pasid_table); + static void __iommu_detach_device(struct iommu_domain *domain, struct device *dev) { diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 0ff5111..491a011 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -131,6 +131,15 @@ struct iommu_dm_region { int prot; }; +struct pasid_table_info { + __u64 ptr; /* PASID table ptr */ + __u64 size; /* PASID table size*/ + __u32 model; /* magic number */ +#define INTEL_IOMMU (1 << 0) +#define ARM_SMMU (1 << 1) + __u8 opaque[];/* IOMMU-specific details */ +}; + #ifdef CONFIG_IOMMU_API /** @@ -159,6 +168,8 @@ struct iommu_dm_region { * @domain_get_windows: Return the number of windows for a domain * @of_xlate: add OF master IDs to iommu grouping * @pgsize_bitmap: bitmap of all possible supported page sizes + * @bind_pasid_table: bind pasid table pointer for guest SVM + * @unbind_pasid_table: unbind pasid table pointer and restore defaults */ struct iommu_ops { bool (*capable)(enum iommu_cap); @@ -200,6 +211,10 @@ struct iommu_ops { u32 (*domain_get_windows)(struct iommu_domain *domain); int (*of_xlate)(struct device *dev, struct of_phandle_args *args); + int (*bind_pasid_table)(struct iommu_domain *domain, struct device *dev, + struct pasid_table_info *pasidt_binfo); + int (*unbind_pasid_table)(struct iommu_domain *domain, + struct device *dev); unsigned long pgsize_bitmap; }; @@ -221,6 +236,10 @@ extern int iommu_attach_device(struct iommu_domain *domain, struct device *dev); extern void iommu_detach_device(struct iommu_domain *domain, struct device *dev); +extern int iommu_bind_pasid_table(struct iommu_domain *domain, + struct device *dev, struct pasid_table_info *pasidt_binfo); +extern int iommu_unbind_pasid_table(struct iommu_domain *domain, + struct device *dev); extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); extern int iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot); @@ -595,6 +614,18 @@ const struct iommu_ops *iommu_get_instance(struct fwnode_handle *fwnode) return NULL; } +static inline +int iommu_bind_pasid_table(struct iommu_domain *domain, struct device *dev, + struct pasid_table_info *pasidt_binfo) +{ + return -EINVAL; +} +static inline +int iommu_unbind_pasid_table(struct iommu_domain *domain, struct device *dev) +{ + return -EINVAL; +} + #endif /* CONFIG_IOMMU_API */ #endif /* __LINUX_IOMMU_H */