From patchwork Wed Jun 21 10:19:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Zhong X-Patchwork-Id: 9801541 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 73E30600C5 for ; Wed, 21 Jun 2017 10:36:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 625402842B for ; Wed, 21 Jun 2017 10:36:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4EA3F28595; Wed, 21 Jun 2017 10:36:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C75D22842B for ; Wed, 21 Jun 2017 10:36:11 +0000 (UTC) Received: from localhost ([::1]:52958 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dNcza-0007rQ-Tc for patchwork-qemu-devel@patchwork.kernel.org; Wed, 21 Jun 2017 06:36:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55922) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dNckb-0002gd-DF for qemu-devel@nongnu.org; Wed, 21 Jun 2017 06:20:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dNcka-0005Dh-2I for qemu-devel@nongnu.org; Wed, 21 Jun 2017 06:20:41 -0400 Received: from mga14.intel.com ([192.55.52.115]:6553) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dNckZ-0004zB-JS for qemu-devel@nongnu.org; Wed, 21 Jun 2017 06:20:39 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Jun 2017 03:20:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,368,1493708400"; d="scan'208";a="983451197" Received: from yangzhon-virtual.bj.intel.com ([10.238.145.52]) by orsmga003.jf.intel.com with ESMTP; 21 Jun 2017 03:20:37 -0700 From: Yang Zhong To: pbonzini@redhat.com Date: Wed, 21 Jun 2017 18:19:59 +0800 Message-Id: <1498040401-16361-14-git-send-email-yang.zhong@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498040401-16361-1-git-send-email-yang.zhong@intel.com> References: <1498040401-16361-1-git-send-email-yang.zhong@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [PATCH 13/15] tcg: disable tcg in CPUX86State struct X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , anthony.xu@intel.com, qemu-devel@nongnu.org, a.rigo@virtualopensystems.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add the CONFIG_TCG for CPU_COMMON_TLB in the CPUX86State struct. Signed-off-by: Yang Zhong --- include/exec/cpu-defs.h | 4 +++- target/i386/cpu.h | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5f4e303..bc8e7f8 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -25,7 +25,9 @@ #include "qemu/host-utils.h" #include "qemu/queue.h" +#ifdef CONFIG_TCG #include "tcg-target.h" +#endif #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif @@ -54,7 +56,7 @@ typedef uint64_t target_ulong; #error TARGET_LONG_SIZE undefined #endif -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 229b216..d67b601 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -52,7 +52,9 @@ #include "exec/cpu-defs.h" +#ifdef CONFIG_TCG #include "fpu/softfloat.h" +#endif #define R_EAX 0 #define R_ECX 1 @@ -1130,8 +1132,9 @@ typedef struct CPUX86State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - +#ifdef CONFIG_TCG CPU_COMMON +#endif /* Fields after CPU_COMMON are preserved across CPU reset. */