From patchwork Wed Jun 21 10:20:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Zhong X-Patchwork-Id: 9801483 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 35357600C5 for ; Wed, 21 Jun 2017 10:31:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2342B2851D for ; Wed, 21 Jun 2017 10:31:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 15ED428591; Wed, 21 Jun 2017 10:31:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D20D2851D for ; Wed, 21 Jun 2017 10:31:43 +0000 (UTC) Received: from localhost ([::1]:52928 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dNcvE-0003Bx-6q for patchwork-qemu-devel@patchwork.kernel.org; Wed, 21 Jun 2017 06:31:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dNckg-0002j8-7Y for qemu-devel@nongnu.org; Wed, 21 Jun 2017 06:20:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dNcke-0005Fl-TA for qemu-devel@nongnu.org; Wed, 21 Jun 2017 06:20:46 -0400 Received: from mga14.intel.com ([192.55.52.115]:6553) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dNcke-0004zB-HB for qemu-devel@nongnu.org; Wed, 21 Jun 2017 06:20:44 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Jun 2017 03:20:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,368,1493708400"; d="scan'208";a="983451202" Received: from yangzhon-virtual.bj.intel.com ([10.238.145.52]) by orsmga003.jf.intel.com with ESMTP; 21 Jun 2017 03:20:39 -0700 From: Yang Zhong To: pbonzini@redhat.com Date: Wed, 21 Jun 2017 18:20:00 +0800 Message-Id: <1498040401-16361-15-git-send-email-yang.zhong@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498040401-16361-1-git-send-email-yang.zhong@intel.com> References: <1498040401-16361-1-git-send-email-yang.zhong@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [PATCH 14/15] tcg: add the CONFIG_TCG for header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , anthony.xu@intel.com, qemu-devel@nongnu.org, a.rigo@virtualopensystems.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add the CONFIG_TCG for exec-all.h. Since function tlb_set_page_with_attrs() is defined in ./accel/tcg/cputlb.c, which will be disabled if tcg is disabled. This function need be implemented in accel/stubs/tcg-stub.c for disable-tcg. Signed-off-by: Yang Zhong --- accel/stubs/tcg-stub.c | 6 +++++ include/exec/cputlb.h | 2 +- include/exec/exec-all.h | 53 ++++++++++++++++++++++++--------------------- include/exec/helper-proto.h | 2 ++ 4 files changed, 37 insertions(+), 26 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 85b0239..a189493 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -63,6 +63,12 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc) return false; } +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, target_ulong size) +{ +} + void update_fp_status(CPUX86State *env) { } diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f94178..cf296d9 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -19,7 +19,7 @@ #ifndef CPUTLB_H #define CPUTLB_H -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 87ae10b..f5d01eb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -82,6 +82,34 @@ void cpu_reloading_memory_map(void); * Note that with KVM only one address space is supported. */ void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx); +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @vaddr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @vaddr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, target_ulong size); +#endif + +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ /** * tlb_flush_page: @@ -205,31 +233,6 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); * depend on when the guests translation ends the TB. */ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @vaddr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @vaddr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, target_ulong size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 954bef8..417c7b0 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -28,7 +28,9 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ #include "helper.h" #include "trace/generated-helpers.h" +#ifdef CONFIG_TCG #include "tcg-runtime.h" +#endif #undef DEF_HELPER_FLAGS_0 #undef DEF_HELPER_FLAGS_1