From patchwork Thu Jun 22 17:48:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 9805037 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C3B92600C5 for ; Thu, 22 Jun 2017 17:51:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B3F9228709 for ; Thu, 22 Jun 2017 17:51:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A8AAB2870C; Thu, 22 Jun 2017 17:51:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 28CEF28709 for ; Thu, 22 Jun 2017 17:51:31 +0000 (UTC) Received: from localhost ([::1]:60299 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6GQ-0004h8-E8 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Jun 2017 13:51:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40553) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6EB-0003Em-NC for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:49:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dO6E7-0001zL-Q0 for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:49:11 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:53772 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6E7-0001zB-DZ for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:49:07 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5MHn5I4009975; Thu, 22 Jun 2017 19:49:05 +0200 Received: from localhost (unknown [31.210.182.235]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 1D1B210EA; Thu, 22 Jun 2017 19:48:59 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Thu, 22 Jun 2017 20:48:58 +0300 Message-Id: <149815373864.1830.11327265472101278016.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149815338558.1830.8107719559183631163.stgit@frigg.lan> References: <149815338558.1830.8107719559183631163.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5MHn5I4009975 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v7 11/26] target: [tcg, i386] Refactor disas_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Peter Crosthwaite , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova --- target/i386/translate.c | 72 +++++++++++++++++++++++++++++++---------------- 1 file changed, 47 insertions(+), 25 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 04d65b8416..34e7cf6788 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4436,16 +4436,17 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContextBase *db, CPUState *cpu) { - DisasContextBase *db = &s->base; + DisasContext *s = container_of(db, DisasContext, base); + CPUX86State *env = cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start = db->pc_next; s->pc_start = s->pc = pc_start; prefixes = 0; @@ -8494,10 +8495,50 @@ static BreakpointCheckType i386_trblock_breakpoint_check( } } +static target_ulong i386_trblock_disas_insn(DisasContextBase *db, CPUState *cpu) +{ + DisasContext *dc = container_of(db, DisasContext, base); + target_ulong pc_next = disas_insn(db, cpu); + + if (db->is_jmp) { + return pc_next; + } + + if (dc->tf || (db->tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + change to be happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + db->is_jmp = DJ_TOO_MANY; + } else if ((db->tb->cflags & CF_USE_ICOUNT) + && ((db->pc_next & TARGET_PAGE_MASK) + != ((db->pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (db->pc_next & ~TARGET_PAGE_MASK) == 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + db->is_jmp = DJ_TOO_MANY; + } else if ((pc_next - db->pc_first) >= (TARGET_PAGE_SIZE - 32)) { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + db->is_jmp = DJ_TOO_MANY; + } + + return pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - CPUX86State *env = cpu->env_ptr; DisasContext dc1, *dc = &dc1; DisasContextBase *db = &dc1.base; CPUBreakpoint *bp; @@ -8547,39 +8588,20 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) gen_io_start(cpu_env); } - db->pc_next = disas_insn(env, dc, db->pc_next); + db->pc_next = i386_trblock_disas_insn(db, cpu); /* stop translation if indicated */ if (db->is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || db->singlestep_enabled || - (db->tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(db->pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((db->pc_next & TARGET_PAGE_MASK) - != ((db->pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) - || (db->pc_next & ~TARGET_PAGE_MASK) == 0)) { + if (db->singlestep_enabled) { gen_jmp_im(db->pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (db->pc_next - db->pc_first) >= (TARGET_PAGE_SIZE - 32) || num_insns >= max_insns) { gen_jmp_im(db->pc_next - dc->cs_base); gen_eob(dc);