From patchwork Sun Jun 25 09:56:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 9808031 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2476B6038C for ; Sun, 25 Jun 2017 09:57:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07BF3205AD for ; Sun, 25 Jun 2017 09:57:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EABAE2868F; Sun, 25 Jun 2017 09:57:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CAF22205AD for ; Sun, 25 Jun 2017 09:57:30 +0000 (UTC) Received: from localhost ([::1]:41893 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4IL-0006ou-FV for patchwork-qemu-devel@patchwork.kernel.org; Sun, 25 Jun 2017 05:57:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4HU-0006n3-RI for qemu-devel@nongnu.org; Sun, 25 Jun 2017 05:56:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dP4HR-0007Bh-Q3 for qemu-devel@nongnu.org; Sun, 25 Jun 2017 05:56:36 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:48772 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4HR-0007BX-8u; Sun, 25 Jun 2017 05:56:33 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5P9uTJk020234; Sun, 25 Jun 2017 11:56:29 +0200 Received: from localhost (unknown [132.68.53.125]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 5367B5E; Sun, 25 Jun 2017 11:56:23 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Sun, 25 Jun 2017 12:56:22 +0300 Message-Id: <149838458211.6497.11741295397438731209.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149838022308.6497.2104916050645246693.stgit@frigg.lan> References: <149838022308.6497.2104916050645246693.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5P9uTJk020234 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v9 18/26] target: [tcg, arm] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova --- target/arm/translate-a64.c | 51 +++++++++++++++----------- target/arm/translate.c | 87 ++++++++++++++++++++++++-------------------- 2 files changed, 78 insertions(+), 60 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8d48251321..1959f27377 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11202,21 +11202,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, - TranslationBlock *tb) +static void aarch64_trblock_init_disas_context(DisasContextBase *db, + CPUState *cpu) { - CPUState *cs = CPU(cpu); - CPUARMState *env = &cpu->env; DisasContext *dc = container_of(db, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - db->tb = tb; - db->pc_first = tb->pc; - db->pc_next = db->pc_first; - db->is_jmp = DJ_NEXT; - db->num_insns = 0; - db->singlestep_enabled = cs->singlestep_enabled; + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); dc->pc = db->pc_first; dc->condjmp = 0; @@ -11229,20 +11220,20 @@ void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; + dc->be_data = ARM_TBFLAG_BE_DATA(db->tb->flags) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); - dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags); - dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags); + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(db->tb->flags)); + dc->tbi0 = ARM_TBFLAG_TBI0(db->tb->flags); + dc->tbi1 = ARM_TBFLAG_TBI1(db->tb->flags); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags); + dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(db->tb->flags); dc->vec_len = 0; dc->vec_stride = 0; - dc->cp_regs = cpu->cp_regs; + dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -11260,12 +11251,30 @@ void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active = ARM_TBFLAG_SS_ACTIVE(db->tb->flags); + dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(db->tb->flags); dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); init_tmp_a64_array(dc); +} + +void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, + TranslationBlock *tb) +{ + CPUState *cs = CPU(cpu); + CPUARMState *env = &cpu->env; + DisasContext *dc = container_of(db, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + db->tb = tb; + db->pc_first = tb->pc; + db->pc_next = db->pc_first; + db->is_jmp = DISAS_NEXT; + db->num_insns = 0; + db->singlestep_enabled = cs->singlestep_enabled; + aarch64_trblock_init_disas_context(db, cs); next_page_start = (db->pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = tb->cflags & CF_COUNT_MASK; diff --git a/target/arm/translate.c b/target/arm/translate.c index 19d042d843..c469bc70ac 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11823,33 +11823,11 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) return false; } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +static void arm_trblock_init_disas_context(DisasContextBase *db, CPUState *cpu) { + DisasContext *dc = container_of(db, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = arm_env_get_cpu(env); - DisasContext dc1, *dc = &dc1; - DisasContextBase *db = &dc->base; - target_ulong next_page_start; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(db, arm_cpu, tb); - return; - } - - db->tb = tb; - db->pc_first = tb->pc; - db->pc_next = db->pc_first; - db->is_jmp = DJ_NEXT; - db->num_insns = 0; - db->singlestep_enabled = cpu->singlestep_enabled; dc->pc = db->pc_first; dc->condjmp = 0; @@ -11860,23 +11838,23 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) */ dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb = ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb = ARM_TBFLAG_THUMB(db->tb->flags); + dc->sctlr_b = ARM_TBFLAG_SCTLR_B(db->tb->flags); + dc->be_data = ARM_TBFLAG_BE_DATA(db->tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(db->tb->flags) & 0xf) << 1; + dc->condexec_cond = ARM_TBFLAG_CONDEXEC(db->tb->flags) >> 4; + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(db->tb->flags)); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->ns = ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags); + dc->ns = ARM_TBFLAG_NS(db->tb->flags); + dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(db->tb->flags); + dc->vfp_enabled = ARM_TBFLAG_VFPEN(db->tb->flags); + dc->vec_len = ARM_TBFLAG_VECLEN(db->tb->flags); + dc->vec_stride = ARM_TBFLAG_VECSTRIDE(db->tb->flags); + dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(db->tb->flags); + dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(db->tb->flags); dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; @@ -11895,10 +11873,41 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active = ARM_TBFLAG_SS_ACTIVE(db->tb->flags); + dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(db->tb->flags); dc->is_ldex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); + DisasContext dc1, *dc = &dc1; + DisasContextBase *db = &dc->base; + target_ulong next_page_start; + int max_insns; + bool end_of_page; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/etc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(db, arm_cpu, tb); + return; + } + + db->tb = tb; + db->pc_first = tb->pc; + db->pc_next = db->pc_first; + db->is_jmp = DISAS_NEXT; + db->num_insns = 0; + db->singlestep_enabled = cpu->singlestep_enabled; + arm_trblock_init_disas_context(db, cpu); + cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32();