| Message ID | 149838531005.6497.12362377034456580175.stgit@frigg.lan (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Lluís Vilanova <vilanova@ac.upc.edu> writes: > Incrementally paves the way towards using the generic instruction translation > loop. > > Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> > --- > target/arm/translate-a64.c | 11 +++++++++-- > target/arm/translate.c | 36 +++++++++++++++++++++--------------- > 2 files changed, 30 insertions(+), 17 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 1959f27377..bfc2cdabb5 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -11259,6 +11259,14 @@ static void aarch64_trblock_init_disas_context(DisasContextBase *db, > init_tmp_a64_array(dc); > } > > +static void aarch64_trblock_insn_start(DisasContextBase *db, CPUState *cpu) > +{ > + DisasContext *dc = container_of(db, DisasContext, base); > + > + dc->insn_start_idx = tcg_op_buf_count(); > + tcg_gen_insn_start(dc->pc, 0, 0); > +} > + > void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, > TranslationBlock *tb) > { > @@ -11291,8 +11299,7 @@ void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, > > do { > db->num_insns++; > - dc->insn_start_idx = tcg_op_buf_count(); > - tcg_gen_insn_start(dc->pc, 0, 0); > + aarch64_trblock_insn_start(db, cs); > > if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { > CPUBreakpoint *bp; > diff --git a/target/arm/translate.c b/target/arm/translate.c > index ae3f772446..18b0e8fbb6 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -11934,6 +11934,26 @@ static void arm_trblock_tb_start(DisasContextBase *db, CPUState *cpu) > } > } > > +static void arm_trblock_insn_start(DisasContextBase *db, CPUState *cpu) > +{ > + DisasContext *dc = container_of(db, DisasContext, base); > + > + dc->insn_start_idx = tcg_op_buf_count(); > + tcg_gen_insn_start(dc->pc, > + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), > + 0); > + > +#ifdef CONFIG_USER_ONLY > + /* Intercept jump to the magic kernel page. */ > + if (dc->pc >= 0xffff0000) { > + /* We always get here via a jump, so know we are not in a > + conditional execution block. */ > + gen_exception_internal(EXCP_KERNEL_TRAP); > + dc->is_jmp = DJ_EXC; This fails to build. > + } > +#endif > +} > + > /* generate intermediate code for basic block 'tb'. */ > void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) > { > @@ -11981,21 +12001,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) > > do { > db->num_insns++; > - dc->insn_start_idx = tcg_op_buf_count(); > - tcg_gen_insn_start(dc->pc, > - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), > - 0); > - > -#ifdef CONFIG_USER_ONLY > - /* Intercept jump to the magic kernel page. */ > - if (dc->pc >= 0xffff0000) { > - /* We always get here via a jump, so know we are not in a > - conditional execution block. */ > - gen_exception_internal(EXCP_KERNEL_TRAP); > - dc->is_jmp = DJ_EXC; > - break; > - } > -#endif > + arm_trblock_insn_start(db, cpu); > > if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { > CPUBreakpoint *bp; -- Alex Bennée
On 06/25/2017 03:08 AM, Lluís Vilanova wrote: > +static void arm_trblock_insn_start(DisasContextBase *db, CPUState *cpu) > +{ > + DisasContext *dc = container_of(db, DisasContext, base); > + > + dc->insn_start_idx = tcg_op_buf_count(); > + tcg_gen_insn_start(dc->pc, > + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), > + 0); > + > +#ifdef CONFIG_USER_ONLY > + /* Intercept jump to the magic kernel page. */ > + if (dc->pc >= 0xffff0000) { > + /* We always get here via a jump, so know we are not in a > + conditional execution block. */ > + gen_exception_internal(EXCP_KERNEL_TRAP); > + dc->is_jmp = DJ_EXC; > + } > +#endif > +} I think this DJ_EXC block is better placed at the start of disas_insn. It is, however, the answer to one of my questions re patch 4/26. r~
Richard Henderson writes: > On 06/25/2017 03:08 AM, Lluís Vilanova wrote: >> +static void arm_trblock_insn_start(DisasContextBase *db, CPUState *cpu) >> +{ >> + DisasContext *dc = container_of(db, DisasContext, base); >> + >> + dc->insn_start_idx = tcg_op_buf_count(); >> + tcg_gen_insn_start(dc->pc, >> + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), >> + 0); >> + >> +#ifdef CONFIG_USER_ONLY >> + /* Intercept jump to the magic kernel page. */ >> + if (dc->pc >= 0xffff0000) { >> + /* We always get here via a jump, so know we are not in a >> + conditional execution block. */ >> + gen_exception_internal(EXCP_KERNEL_TRAP); >> + dc->is_jmp = DJ_EXC; >> + } >> +#endif >> +} > I think this DJ_EXC block is better placed at the start of disas_insn. > It is, however, the answer to one of my questions re patch 4/26. It cannot, because DJ_EXC make the generic code break out of trasnlation before doing anything else, which is what the original code does. Cheers, Lluis
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1959f27377..bfc2cdabb5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11259,6 +11259,14 @@ static void aarch64_trblock_init_disas_context(DisasContextBase *db, init_tmp_a64_array(dc); } +static void aarch64_trblock_insn_start(DisasContextBase *db, CPUState *cpu) +{ + DisasContext *dc = container_of(db, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, TranslationBlock *tb) { @@ -11291,8 +11299,7 @@ void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, do { db->num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_trblock_insn_start(db, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; diff --git a/target/arm/translate.c b/target/arm/translate.c index ae3f772446..18b0e8fbb6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11934,6 +11934,26 @@ static void arm_trblock_tb_start(DisasContextBase *db, CPUState *cpu) } } +static void arm_trblock_insn_start(DisasContextBase *db, CPUState *cpu) +{ + DisasContext *dc = container_of(db, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >= 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->is_jmp = DJ_EXC; + } +#endif +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11981,21 +12001,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) do { db->num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); - -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >= 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp = DJ_EXC; - break; - } -#endif + arm_trblock_insn_start(db, cpu); if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { CPUBreakpoint *bp;
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> --- target/arm/translate-a64.c | 11 +++++++++-- target/arm/translate.c | 36 +++++++++++++++++++++--------------- 2 files changed, 30 insertions(+), 17 deletions(-)