From patchwork Sun Jun 25 10:12:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 9808043 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8E1BB603F3 for ; Sun, 25 Jun 2017 10:13:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73F7727F7F for ; Sun, 25 Jun 2017 10:13:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6879428468; Sun, 25 Jun 2017 10:13:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B9DA727F7F for ; Sun, 25 Jun 2017 10:13:27 +0000 (UTC) Received: from localhost ([::1]:41942 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4Xl-0004rx-HD for patchwork-qemu-devel@patchwork.kernel.org; Sun, 25 Jun 2017 06:13:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4X7-0004pp-Kn for qemu-devel@nongnu.org; Sun, 25 Jun 2017 06:12:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dP4X2-0004rM-KJ for qemu-devel@nongnu.org; Sun, 25 Jun 2017 06:12:45 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:38241 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dP4X2-0004rA-3s; Sun, 25 Jun 2017 06:12:40 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5PACcJD020515; Sun, 25 Jun 2017 12:12:38 +0200 Received: from localhost (unknown [132.68.53.125]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 1F40313BC; Sun, 25 Jun 2017 12:12:33 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Sun, 25 Jun 2017 13:12:32 +0300 Message-Id: <149838555190.6497.14794381660566656791.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149838022308.6497.2104916050645246693.stgit@frigg.lan> References: <149838022308.6497.2104916050645246693.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5PACcJD020515 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v9 22/26] target: [tcg, arm] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova --- target/arm/translate-a64.c | 59 ++++++++++++++++++++++++++------------- target/arm/translate.c | 66 +++++++++++++++++++++++++++++--------------- 2 files changed, 82 insertions(+), 43 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bfc2cdabb5..4321767355 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11267,6 +11267,29 @@ static void aarch64_trblock_insn_start(DisasContextBase *db, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } +static BreakpointCheckType aarch64_trblock_breakpoint_check( + DisasContextBase *db, CPUState *cpu, const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(db, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + db->is_jmp = DJ_UPDATE; + return BC_HIT_INSN; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc += 4; + return BC_HIT_TB; + } +} + void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, TranslationBlock *tb) { @@ -11275,6 +11298,7 @@ void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, DisasContext *dc = container_of(db, DisasContext, base); target_ulong next_page_start; int max_insns; + CPUBreakpoint *bp; db->tb = tb; db->pc_first = tb->pc; @@ -11301,29 +11325,24 @@ void gen_intermediate_code_a64(DisasContextBase *db, ARMCPU *cpu, db->num_insns++; aarch64_trblock_insn_start(db, cs); - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - db->is_jmp = DJ_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - dc->pc += 4; - goto done_generating; - } + bp = NULL; + do { + bp = cpu_breakpoint_get(cs, db->pc_next, bp); + if (unlikely(bp)) { + BreakpointCheckType bp_check = + aarch64_trblock_breakpoint_check(db, cs, bp); + if (bp_check == BC_HIT_INSN) { + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one BP in a + * single address, we can simply use a bool here. + */ break; + } else { + goto done_generating; } } - } + } while (bp != NULL); if (db->num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(cpu_env); diff --git a/target/arm/translate.c b/target/arm/translate.c index 18b0e8fbb6..a7fcaf2a21 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11954,6 +11954,33 @@ static void arm_trblock_insn_start(DisasContextBase *db, CPUState *cpu) #endif } +static BreakpointCheckType arm_trblock_breakpoint_check(DisasContextBase *db, + CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(db, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + db->is_jmp = DJ_UPDATE; + return BC_HIT_INSN; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc += 2; + return BC_HIT_TB; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { @@ -11964,6 +11991,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) target_ulong next_page_start; int max_insns; bool end_of_page; + CPUBreakpoint *bp; /* generate intermediate code */ @@ -12003,32 +12031,24 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) db->num_insns++; arm_trblock_insn_start(db, cpu); - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc == dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be executed */ - db->is_jmp = DJ_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length to - * avoid disassembler error messages */ - dc->pc += 2; - goto done_generating; - } + bp = NULL; + do { + bp = cpu_breakpoint_get(cpu, db->pc_next, bp); + if (unlikely(bp)) { + BreakpointCheckType bp_check = arm_trblock_breakpoint_check( + db, cpu, bp); + if (bp_check == BC_HIT_INSN) { + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one BP in a + * single address, we can simply use a bool here. + */ break; + } else { + goto done_generating; } } - } + } while (bp != NULL); if (db->num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(cpu_env);