From patchwork Wed Jun 28 13:57:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 9814359 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EBD2960383 for ; Wed, 28 Jun 2017 13:58:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DBDDE28565 for ; Wed, 28 Jun 2017 13:58:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D0B2C2856A; Wed, 28 Jun 2017 13:58:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 214F628565 for ; Wed, 28 Jun 2017 13:58:25 +0000 (UTC) Received: from localhost ([::1]:33533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDU9-0003Mg-1F for patchwork-qemu-devel@patchwork.kernel.org; Wed, 28 Jun 2017 09:58:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38244) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDTY-0003MI-27 for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:57:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQDTU-0001gu-Ul for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:57:48 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:34005) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQDTU-0001gI-Fh; Wed, 28 Jun 2017 09:57:44 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDveuC028318; Wed, 28 Jun 2017 15:57:40 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id E65CA165; Wed, 28 Jun 2017 15:57:34 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:57:33 +0300 Message-Id: <149865825357.17063.13113603039704787150.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDveuC028318 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 25/29] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova --- target/arm/translate.c | 195 ++++++++++++++++++++++++++---------------------- 1 file changed, 104 insertions(+), 91 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7ab09a7e5f..ef0b870a2f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12018,103 +12018,21 @@ static target_ulong arm_trblock_translate_insn(DisasContextBase *dcbase, return dc->pc; } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +static void arm_trblock_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc = &dc1; - int max_insns; - - /* generate intermediate code */ + DisasContext *dc = container_of(dcbase, DisasContext, base); - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cpu, tb); + if (dc->base.is_jmp == DISAS_SKIP) { return; } - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cpu->singlestep_enabled; - arm_trblock_init_disas_context(&dc->base, cpu); - - - arm_trblock_init_globals(&dc->base, cpu); - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; + if ((dc->base.tb->cflags & CF_LAST_IO) && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. */ + cpu_abort(cpu, "IO on conditional branch instruction"); } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_trblock_tb_start(&dc->base, cpu); - - do { - dc->base.num_insns++; - arm_trblock_insn_start(&dc->base, cpu); - - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - BreakpointCheckType bp_check = - arm_trblock_breakpoint_check(&dc->base, cpu, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - dc->base.pc_next = arm_trblock_translate_insn(&dc->base, cpu); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >= max_insns)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - if (dc->base.is_jmp != DISAS_SKIP) { - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cpu, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. */ + cpu_abort(cpu, "IO on conditional branch instruction"); } /* At this stage dc->condjmp will only be set when the skipped @@ -12218,6 +12136,101 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc1, *dc = &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/etc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cpu, tb); + return; + } + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cpu->singlestep_enabled; + arm_trblock_init_disas_context(&dc->base, cpu); + + + arm_trblock_init_globals(&dc->base, cpu); + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_trblock_tb_start(&dc->base, cpu); + + do { + dc->base.num_insns++; + arm_trblock_insn_start(&dc->base, cpu); + + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc == dc->base.pc_next) { + BreakpointCheckType bp_check = + arm_trblock_breakpoint_check(&dc->base, cpu, bp); + switch (bp_check) { + case BC_MISS: + /* Target ignored this breakpoint, go to next */ + break; + case BC_HIT_INSN: + /* Hit, keep translating */ + /* + * TODO: if we're never going to have more than one + * BP in a single address, we can simply use a + * bool here. + */ + goto done_breakpoints; + case BC_HIT_TB: + /* Hit, end TB */ + goto done_generating; + default: + g_assert_not_reached(); + } + } + } + } + done_breakpoints: + + if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + gen_io_start(); + } + + dc->base.pc_next = arm_trblock_translate_insn(&dc->base, cpu); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >= max_insns)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + arm_trblock_tb_stop(&dc->base, cpu); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); } done_generating: