From patchwork Thu Jun 29 05:49:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9816513 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 844B16020A for ; Thu, 29 Jun 2017 11:58:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA4BA285FF for ; Thu, 29 Jun 2017 11:57:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9EC762860B; Thu, 29 Jun 2017 11:57:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 20562285FF for ; Thu, 29 Jun 2017 11:57:57 +0000 (UTC) Received: from localhost ([::1]:38508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQY56-0006pp-BB for patchwork-qemu-devel@patchwork.kernel.org; Thu, 29 Jun 2017 07:57:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQY45-0006o1-5z for qemu-devel@nongnu.org; Thu, 29 Jun 2017 07:56:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQY41-00076M-5N for qemu-devel@nongnu.org; Thu, 29 Jun 2017 07:56:53 -0400 Received: from mga05.intel.com ([192.55.52.43]:1646) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dQY40-00075b-QK for qemu-devel@nongnu.org; Thu, 29 Jun 2017 07:56:49 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP; 29 Jun 2017 04:56:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,280,1496127600"; d="scan'208";a="986649979" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.74]) by orsmga003.jf.intel.com with ESMTP; 29 Jun 2017 04:56:45 -0700 From: Lan Tianyu To: qemu-devel@nongnu.org, xen-devel@lists.xensource.com Date: Thu, 29 Jun 2017 01:49:54 -0400 Message-Id: <1498715394-16402-4-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1498715394-16402-1-git-send-email-tianyu.lan@intel.com> References: <1498715394-16402-1-git-send-email-tianyu.lan@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH 3/3] msi: Handle remappable format interrupt request X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , kevin.tian@intel.com, sstabellini@kernel.org, mst@redhat.com, anthony.perard@citrix.com, marcel@redhat.com, Chao Gao Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao According to VT-d spec Interrupt Remapping and Interrupt Posting -> Interrupt Remapping -> Interrupt Request Formats On Intel 64 Platforms, fields of MSI data register have changed. This patch avoids wrongly regarding a remappable format interrupt request as an interrupt binded with an event channel. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu Acked-by: Anthony PERARD --- hw/pci/msi.c | 5 +++-- hw/pci/msix.c | 4 +++- hw/xen/xen_pt_msi.c | 2 +- include/hw/xen/xen.h | 2 +- xen-hvm-stub.c | 2 +- xen-hvm.c | 8 +++++++- 6 files changed, 16 insertions(+), 7 deletions(-) diff --git a/hw/pci/msi.c b/hw/pci/msi.c index a87b227..3713ea6 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -289,7 +289,7 @@ void msi_reset(PCIDevice *dev) static bool msi_is_masked(const PCIDevice *dev, unsigned int vector) { uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev)); - uint32_t mask, data; + uint32_t mask, data, addr_lo; bool msi64bit = flags & PCI_MSI_FLAGS_64BIT; assert(vector < PCI_MSI_VECTORS_MAX); @@ -298,7 +298,8 @@ static bool msi_is_masked(const PCIDevice *dev, unsigned int vector) } data = pci_get_word(dev->config + msi_data_off(dev, msi64bit)); - if (xen_is_pirq_msi(data)) { + addr_lo = pci_get_long(dev->config + msi_address_lo_off(dev)); + if (xen_is_pirq_msi(addr_lo, data)) { return false; } diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 0ec1cb1..6dda83c 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -81,9 +81,11 @@ static bool msix_vector_masked(PCIDevice *dev, unsigned int vector, bool fmask) { unsigned offset = vector * PCI_MSIX_ENTRY_SIZE; uint8_t *data = &dev->msix_table[offset + PCI_MSIX_ENTRY_DATA]; + uint8_t *addr_lo = &dev->msix_table[offset + PCI_MSIX_ENTRY_LOWER_ADDR]; /* MSIs on Xen can be remapped into pirqs. In those cases, masking * and unmasking go through the PV evtchn path. */ - if (xen_enabled() && xen_is_pirq_msi(pci_get_long(data))) { + if (xen_enabled() && xen_is_pirq_msi(pci_get_long(addr_lo), + pci_get_long(data))) { return false; } return fmask || dev->msix_table[offset + PCI_MSIX_ENTRY_VECTOR_CTRL] & diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c index 26a69d9..68da0e4 100644 --- a/hw/xen/xen_pt_msi.c +++ b/hw/xen/xen_pt_msi.c @@ -114,7 +114,7 @@ static int msi_msix_setup(XenPCIPassthroughState *s, assert((!is_msix && msix_entry == 0) || is_msix); - if (xen_is_pirq_msi(data)) { + if (xen_is_pirq_msi(addr, data)) { *ppirq = msi_ext_dest_id(addr >> 32) | msi_dest_id(addr); if (!*ppirq) { /* this probably identifies an misconfiguration of the guest, diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h index a8f3afb..b1ef41e 100644 --- a/include/hw/xen/xen.h +++ b/include/hw/xen/xen.h @@ -33,7 +33,7 @@ int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num); void xen_piix3_set_irq(void *opaque, int irq_num, int level); void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len); void xen_hvm_inject_msi(uint64_t addr, uint32_t data); -int xen_is_pirq_msi(uint32_t msi_data); +int xen_is_pirq_msi(uint32_t msi_addr_lo, uint32_t msi_data); qemu_irq *xen_interrupt_controller_init(void); diff --git a/xen-hvm-stub.c b/xen-hvm-stub.c index c500325..a3a3bb3 100644 --- a/xen-hvm-stub.c +++ b/xen-hvm-stub.c @@ -31,7 +31,7 @@ void xen_hvm_inject_msi(uint64_t addr, uint32_t data) { } -int xen_is_pirq_msi(uint32_t msi_data) +int xen_is_pirq_msi(uint32_t msi_addr_lo, uint32_t msi_data) { return 0; } diff --git a/xen-hvm.c b/xen-hvm.c index 0892361..9f1a7bd 100644 --- a/xen-hvm.c +++ b/xen-hvm.c @@ -146,8 +146,14 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len) } } -int xen_is_pirq_msi(uint32_t msi_data) +int xen_is_pirq_msi(uint32_t msi_addr_lo, uint32_t msi_data) { + /* If the MSI address is configured in remapping format, the MSI will not + * be remapped into a pirq. + */ + if (msi_addr_lo & MSI_ADDR_IF_MASK) { + return 0; + } /* If vector is 0, the msi is remapped into a pirq, passed as * dest_id. */