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[109.173.19.108]) by smtp.gmail.com with ESMTPSA id r196sm1050903lfe.38.2017.08.13.09.03.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 Aug 2017 09:03:35 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sun, 13 Aug 2017 19:03:22 +0300 Message-Id: <1502640203-15577-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502640203-15577-1-git-send-email-zuban32s@gmail.com> References: <1502640203-15577-1-git-send-email-zuban32s@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v6 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, Aleksandr Bezzubikov , kevin@koconnor.net, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/dev-pci.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..0dc5556 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,53 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + * + * QEMU-specific vendor(Red Hat)-specific capability. + * It's intended to provide some hints for firmware to init PCI devices. + * + * Its structure is shown below: + * + * Header: + * + * u8 id; Standard PCI Capability Header field + * u8 next; Standard PCI Capability Header field + * u8 len; Standard PCI Capability Header field + * u8 type; Red Hat vendor-specific capability type + * Data: + * + * u32 bus_res; minimum bus number to reserve; + * this is necessary for PCI Express Root Ports + * to support PCI bridges hotplug + * u64 io; IO space to reserve + * u32 mem; non-prefetchable memory to reserve + * + * At most of the following two fields may be set to a value + * different from 0xFF...F: + * u32 prefetchable_mem_32; prefetchable memory to reserve (32-bit MMIO) + * u64 prefetchable_mem_64; prefetchable memory to reserve (64-bit MMIO) + * + * If any field value in Data section is 0xFF...F, + * it means that such kind of reservation is not needed and must be ignored. + * +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE_OFFSET 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_RESOURCE_RESERVE 1 + + +/* Offsets of RESOURCE_RESERVE capability fields */ +#define RES_RESERVE_BUS_RES 4 +#define RES_RESERVE_IO 8 +#define RES_RESERVE_MEM 16 +#define RES_RESERVE_PREF_MEM_32 20 +#define RES_RESERVE_PREF_MEM_64 24 +#define RES_RESERVE_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ +