From patchwork Thu Sep 21 13:38:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 9963955 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 47D50600C5 for ; Thu, 21 Sep 2017 13:41:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D2C2290C3 for ; Thu, 21 Sep 2017 13:41:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2B63F2952D; Thu, 21 Sep 2017 13:41:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B8C3F290C3 for ; Thu, 21 Sep 2017 13:41:22 +0000 (UTC) Received: from localhost ([::1]:53771 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv1jG-0000Hz-3Z for patchwork-qemu-devel@patchwork.kernel.org; Thu, 21 Sep 2017 09:41:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv1gc-0007eU-2n for qemu-devel@nongnu.org; Thu, 21 Sep 2017 09:38:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dv1ga-0006r3-H1 for qemu-devel@nongnu.org; Thu, 21 Sep 2017 09:38:38 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:12131) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv1ga-0006qj-6p for qemu-devel@nongnu.org; Thu, 21 Sep 2017 09:38:36 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 7B79982836981; Thu, 21 Sep 2017 14:38:30 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 21 Sep 2017 14:38:33 +0100 From: Yongbok Kim To: Date: Thu, 21 Sep 2017 14:38:09 +0100 Message-ID: <1506001091-8296-6-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506001091-8296-1-git-send-email-yongbok.kim@imgtec.com> References: <1506001091-8296-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 5/7] mips: MIPSCPU model subclasses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Igor Mammedov Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daudé [PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass, mark MIPSCPU abstract, address Eduardo Habkost review] Tested-by: James Hogan Reviewed-by: Eduardo Habkost Signed-off-by: Yongbok Kim --- target/mips/cpu-qom.h | 1 + target/mips/cpu.c | 50 ++++++++++++++++++++++++++++++++++++- target/mips/internal.h | 59 ++++++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 13 +++++----- target/mips/translate_init.c | 58 ++----------------------------------------- 5 files changed, 117 insertions(+), 64 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 3f5bf23..ee58606 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -49,6 +49,7 @@ typedef struct MIPSCPUClass { DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + const struct mips_def_t *cpu_def; } MIPSCPUClass; typedef struct MIPSCPU MIPSCPU; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e3ef835..1a9a3ed 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -146,14 +146,36 @@ static void mips_cpu_initfn(Object *obj) CPUState *cs = CPU(obj); MIPSCPU *cpu = MIPS_CPU(obj); CPUMIPSState *env = &cpu->env; + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); cs->env_ptr = env; + env->cpu_model = mcc->cpu_def; if (tcg_enabled()) { mips_tcg_init(); } } +static char *mips_cpu_type_name(const char *cpu_model) +{ + return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model); +} + +static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + + if (cpu_model == NULL) { + return NULL; + } + + typename = mips_cpu_type_name(cpu_model); + oc = object_class_by_name(typename); + g_free(typename); + return oc; +} + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -166,6 +188,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) mcc->parent_reset = cc->reset; cc->reset = mips_cpu_reset; + cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; cc->do_interrupt = mips_cpu_do_interrupt; cc->cpu_exec_interrupt = mips_cpu_exec_interrupt; @@ -193,14 +216,39 @@ static const TypeInfo mips_cpu_type_info = { .parent = TYPE_CPU, .instance_size = sizeof(MIPSCPU), .instance_init = mips_cpu_initfn, - .abstract = false, + .abstract = true, .class_size = sizeof(MIPSCPUClass), .class_init = mips_cpu_class_init, }; +static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) +{ + MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); + mcc->cpu_def = data; +} + +static void mips_register_cpudef_type(const struct mips_def_t *def) +{ + char *typename = mips_cpu_type_name(def->name); + TypeInfo ti = { + .name = typename, + .parent = TYPE_MIPS_CPU, + .class_init = mips_cpu_cpudef_class_init, + .class_data = (void *)def, + }; + + type_register(&ti); + g_free(typename); +} + static void mips_cpu_register_types(void) { + int i; + type_register_static(&mips_cpu_type_info); + for (i = 0; i < mips_defs_number; i++) { + mips_register_cpudef_type(&mips_defs[i]); + } } type_init(mips_cpu_register_types) diff --git a/target/mips/internal.h b/target/mips/internal.h index cf4c9db..45ded34 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -7,6 +7,65 @@ #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H + +/* MMU types, the first four entries have the same layout as the + CP0C0_MT field. */ +enum mips_mmu_types { + MMU_TYPE_NONE, + MMU_TYPE_R4000, + MMU_TYPE_RESERVED, + MMU_TYPE_FMT, + MMU_TYPE_R3000, + MMU_TYPE_R6000, + MMU_TYPE_R8000 +}; + +struct mips_def_t { + const char *name; + int32_t CP0_PRid; + int32_t CP0_Config0; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config4; + int32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; + int32_t CP0_Config6; + int32_t CP0_Config7; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + int32_t SYNCI_Step; + int32_t CCRes; + int32_t CP0_Status_rw_bitmask; + int32_t CP0_TCStatus_rw_bitmask; + int32_t CP0_SRSCtl; + int32_t CP1_fcr0; + int32_t CP1_fcr31_rw_bitmask; + int32_t CP1_fcr31; + int32_t MSAIR; + int32_t SEGBITS; + int32_t PABITS; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; + int32_t CP0_PageGrain_rw_bitmask; + int32_t CP0_PageGrain; + target_ulong CP0_EBaseWG_rw_bitmask; + int insn_flags; + enum mips_mmu_types mmu_type; +}; + +extern const struct mips_def_t mips_defs[]; +extern const int mips_defs_number; + enum CPUMIPSMSADataFormat { DF_BYTE = 0, DF_HALF, diff --git a/target/mips/translate.c b/target/mips/translate.c index 94c38e8..f7128bc 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20525,16 +20525,15 @@ void cpu_mips_realize_env(CPUMIPSState *env) MIPSCPU *cpu_mips_init(const char *cpu_model) { + ObjectClass *oc; MIPSCPU *cpu; - CPUMIPSState *env; - const mips_def_t *def; - def = cpu_mips_find_by_name(cpu_model); - if (!def) + oc = cpu_class_by_name(TYPE_MIPS_CPU, cpu_model); + if (oc == NULL) { return NULL; - cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU)); - env = &cpu->env; - env->cpu_model = def; + } + + cpu = MIPS_CPU(object_new(object_class_get_name(oc))); object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index 255d25b..8bbded4 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -51,64 +51,9 @@ #define MIPS_CONFIG5 \ ((0 << CP0C5_M)) -/* MMU types, the first four entries have the same layout as the - CP0C0_MT field. */ -enum mips_mmu_types { - MMU_TYPE_NONE, - MMU_TYPE_R4000, - MMU_TYPE_RESERVED, - MMU_TYPE_FMT, - MMU_TYPE_R3000, - MMU_TYPE_R6000, - MMU_TYPE_R8000 -}; - -struct mips_def_t { - const char *name; - int32_t CP0_PRid; - int32_t CP0_Config0; - int32_t CP0_Config1; - int32_t CP0_Config2; - int32_t CP0_Config3; - int32_t CP0_Config4; - int32_t CP0_Config4_rw_bitmask; - int32_t CP0_Config5; - int32_t CP0_Config5_rw_bitmask; - int32_t CP0_Config6; - int32_t CP0_Config7; - target_ulong CP0_LLAddr_rw_bitmask; - int CP0_LLAddr_shift; - int32_t SYNCI_Step; - int32_t CCRes; - int32_t CP0_Status_rw_bitmask; - int32_t CP0_TCStatus_rw_bitmask; - int32_t CP0_SRSCtl; - int32_t CP1_fcr0; - int32_t CP1_fcr31_rw_bitmask; - int32_t CP1_fcr31; - int32_t MSAIR; - int32_t SEGBITS; - int32_t PABITS; - int32_t CP0_SRSConf0_rw_bitmask; - int32_t CP0_SRSConf0; - int32_t CP0_SRSConf1_rw_bitmask; - int32_t CP0_SRSConf1; - int32_t CP0_SRSConf2_rw_bitmask; - int32_t CP0_SRSConf2; - int32_t CP0_SRSConf3_rw_bitmask; - int32_t CP0_SRSConf3; - int32_t CP0_SRSConf4_rw_bitmask; - int32_t CP0_SRSConf4; - int32_t CP0_PageGrain_rw_bitmask; - int32_t CP0_PageGrain; - target_ulong CP0_EBaseWG_rw_bitmask; - int insn_flags; - enum mips_mmu_types mmu_type; -}; - /*****************************************************************************/ /* MIPS CPU definitions */ -static const mips_def_t mips_defs[] = +const mips_def_t mips_defs[] = { { .name = "4Kc", @@ -808,6 +753,7 @@ static const mips_def_t mips_defs[] = #endif }; +const int mips_defs_number = ARRAY_SIZE(mips_defs); static const mips_def_t *cpu_mips_find_by_name (const char *name) {