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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id h3sm1258383lfj.26.2017.11.03.20.46.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 20:46:19 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Fri, 3 Nov 2017 20:45:16 -0700 Message-Id: <1509767121-26925-12-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509767121-26925-1-git-send-email-jcmvbkbc@gmail.com> References: <1509767121-26925-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH 11/16] target/xtensa: drop DisasContext::litbase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP It doesn't help much, always-set bit 0 of the LITBASE SR is easy to compensate with decrement of the l32r immediate argument. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 0460edf61389..fb6a4c979590 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -59,7 +59,6 @@ typedef struct DisasContext { int ring; uint32_t lbeg; uint32_t lend; - TCGv_i32 litbase; int is_jmp; int singlestep_enabled; @@ -266,21 +265,6 @@ static inline bool option_enabled(DisasContext *dc, int opt) return xtensa_option_enabled(dc->config, opt); } -static void init_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - dc->litbase = tcg_temp_local_new_i32(); - tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); - } -} - -static void reset_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_temp_free(dc->litbase); - } -} - static void init_sar_tracker(DisasContext *dc) { dc->sar_5bit = false; @@ -1094,7 +1078,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa); } - init_litbase(&dc); init_sar_tracker(&dc); if (dc.icount) { dc.next_icount = tcg_temp_local_new_i32(); @@ -1169,7 +1152,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && !tcg_op_buf_full()); done: - reset_litbase(&dc); reset_sar_tracker(&dc); if (dc.icount) { tcg_temp_free(dc.next_icount); @@ -1672,12 +1654,13 @@ static void translate_l32r(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { if (gen_window_check1(dc, arg[0])) { - TCGv_i32 tmp = (dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? - tcg_const_i32(dc->raw_arg[1] - 1) : - tcg_const_i32(arg[1]); + TCGv_i32 tmp; if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_gen_add_i32(tmp, tmp, dc->litbase); + tmp = tcg_const_i32(dc->raw_arg[1] - 1); + tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); + } else { + tmp = tcg_const_i32(arg[1]); } tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); tcg_temp_free(tmp);