From patchwork Mon Dec 4 22:25:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Purdie X-Patchwork-Id: 10091677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 358176035E for ; Mon, 4 Dec 2017 22:26:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2722729272 for ; Mon, 4 Dec 2017 22:26:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C0CB29338; Mon, 4 Dec 2017 22:26:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 86AF429272 for ; Mon, 4 Dec 2017 22:26:56 +0000 (UTC) Received: from localhost ([::1]:45533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eLzCR-00045u-RL for patchwork-qemu-devel@patchwork.kernel.org; Mon, 04 Dec 2017 17:26:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eLzBp-0003jn-7F for qemu-devel@nongnu.org; Mon, 04 Dec 2017 17:26:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eLzBo-0005De-5F for qemu-devel@nongnu.org; Mon, 04 Dec 2017 17:26:17 -0500 Received: from 5751f4a1.skybroadband.com ([87.81.244.161]:60537 helo=dan.rpsys.net) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eLzBj-0005A6-Af; Mon, 04 Dec 2017 17:26:11 -0500 Received: from hex ([192.168.3.34]) (authenticated bits=0) by dan.rpsys.net (8.15.2/8.15.2/Debian-3) with ESMTPSA id vB4MPkEo011755 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 4 Dec 2017 22:25:50 GMT Received: from richard by hex with local (Exim 4.86_2) (envelope-from ) id 1eLzBK-0004wC-NP; Mon, 04 Dec 2017 22:25:46 +0000 From: Richard Purdie To: qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Mon, 4 Dec 2017 22:25:43 +0000 Message-Id: <1512426343-18938-1-git-send-email-richard.purdie@linuxfoundation.org> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: clamav-milter 0.99.2 at dan X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.81.244.161 Subject: [Qemu-devel] [PATCH v3] target/ppc: Fix system lockups caused by interrupt_request state corruption X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Purdie , qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Occasionally in Linux guests on x86_64 we're seeing logs like: ppc_set_irq: 0x55b4e0d562f0 n_IRQ 8 level 1 => pending 00000100req 00000004 when they should read: ppc_set_irq: 0x55b4e0d562f0 n_IRQ 8 level 1 => pending 00000100req 00000002 The "00000004" is CPU_INTERRUPT_EXITTB yet the code calls cpu_interrupt(cs, CPU_INTERRUPT_HARD) ("00000002") in this function just before the log message. Something is causing the HARD bit setting to get lost. The knock on effect of losing that bit is the decrementer timer interrupts don't get delivered which causes the guest to sit idle in its idle handler and 'hang'. The issue occurs due to races from code which sets CPU_INTERRUPT_EXITTB. Rather than poking directly into cs->interrupt_request, that code needs to: a) hold BQL b) use the cpu_interrupt() helper This patch fixes the call sites to do this, fixing the hang. The calls are made from a variety of contexts so a helper function is added to handle the necessary locking. This can likely be improved and optimised in the future but it ensures the code is correct and doesn't lockup as it stands today. Signed-off-by: Richard Purdie --- target/ppc/excp_helper.c | 7 +++---- target/ppc/helper_regs.h | 17 +++++++++++++++-- 2 files changed, 18 insertions(+), 6 deletions(-) v3: Fix make check failures v2: Fixes a compile issue with master and ensures BQL is held in one case where it potentially wasn't. diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e6009e70e5..37d2410726 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -207,7 +207,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) "Entering checkstop state\n"); } cs->halted = 1; - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); } if (env->msr_mask & MSR_HVB) { /* ISA specifies HV, but can be delivered to guest with HV clear @@ -940,7 +940,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) if (excp != 0) { CPUState *cs = CPU(ppc_env_get_cpu(env)); - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); raise_exception(env, excp); } } @@ -995,8 +995,7 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) /* No need to raise an exception here, * as rfi is always the last insn of a TB */ - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; - + cpu_interrupt_exittb(cs); /* Reset the reservation */ env->reserve_addr = -1; diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 2627a70176..84fd30c2db 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -20,6 +20,8 @@ #ifndef HELPER_REGS_H #define HELPER_REGS_H +#include "qemu/main-loop.h" + /* Swap temporary saved registers with GPRs */ static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) { @@ -96,6 +98,17 @@ static inline void hreg_compute_hflags(CPUPPCState *env) env->hflags |= env->hflags_nmsr; } +static inline void cpu_interrupt_exittb(CPUState *cs) +{ + if (!qemu_mutex_iothread_locked()) { + qemu_mutex_lock_iothread(); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + qemu_mutex_unlock_iothread(); + } else { + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + } +} + static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) { @@ -114,11 +127,11 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, } if (((value >> MSR_IR) & 1) != msr_ir || ((value >> MSR_DR) & 1) != msr_dr) { - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); } if ((env->mmu_model & POWERPC_MMU_BOOKE) && ((value >> MSR_GS) & 1) != msr_gs) { - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); } if (unlikely((env->flags & POWERPC_FLAG_TGPR) && ((value ^ env->msr) & (1 << MSR_TGPR)))) {