From patchwork Thu Jan 11 02:22:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 10156717 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EC4EC60231 for ; Thu, 11 Jan 2018 02:28:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D86F7286F2 for ; Thu, 11 Jan 2018 02:28:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD37E286FB; Thu, 11 Jan 2018 02:28:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3B04D286F2 for ; Thu, 11 Jan 2018 02:28:21 +0000 (UTC) Received: from localhost ([::1]:59931 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZSbM-0007bz-Ef for patchwork-qemu-devel@patchwork.kernel.org; Wed, 10 Jan 2018 21:28:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48204) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZSWq-0003NT-Uz for qemu-devel@nongnu.org; Wed, 10 Jan 2018 21:23:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZSWp-0008QJ-7P for qemu-devel@nongnu.org; Wed, 10 Jan 2018 21:23:40 -0500 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:43122) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eZSWo-0008PJ-9Y for qemu-devel@nongnu.org; Wed, 10 Jan 2018 21:23:38 -0500 Received: by mail-pf0-x244.google.com with SMTP id e3so16771pfi.10 for ; Wed, 10 Jan 2018 18:23:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lBBzFAIA2xh4zyrMWM0R1i0A+u2qLLwVZpPU2flCzqA=; b=dkEMhQtRxgp7rzVEYVi81gO4hKplKNncsSRbUlGM9g7I0QEquoQ2iMt6KXx021NVKA 0fFSRfU6yRjbTLzLuBkGKaOcB+gNGgHT4VLQIz5TTalC0T3JYDwP9xmZRx6mPeS6aEcz 2IkG8RZtYuyaLHbXRABtfFB/wz+Iprhw6jkcwG2Hm50Admfct8CcSSaVxc9f21ssPMu3 e1qblWkMDFb3UjsAm4l8Ew+yTr4hrK0TNIQKed8tDreQ1uqXV8CHH/zT6+mpM4EBX6k8 6Xa029irN4ieurFoPeKAmOx0vVsKf3S9wR7JAn2HuW8OJuIHR+XT422ogCnW+M9MmBnn 9Gig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lBBzFAIA2xh4zyrMWM0R1i0A+u2qLLwVZpPU2flCzqA=; b=FDpUOqmVfOsHh7MW99DmGAwr+it9T0FpXoyA8iOw3swIb+otW8/W/88Ym0nJGBCxrV FR8HjRrAPUiPtYa4UAhnwszOiw6DhFevkxEn3CnML0F6w6s/yNIB1aSkhCWyfCTI1jwF gaEZun/8yg6hCOae38QcEmqKJF/Hog6BZ1uwgpCwVHoGCNyexTMgZ3bDGLyV83q/tgIQ 9DbOkiQ3wsvdpefntHQuwEYbvbwg1WSrB1Z3BWs87qv4aTRlS+tdWGd6NDgz4BxZ63iO iuBnjQDTOjRLkpGBckSjd4F3vu66NAw0zRKNWZLIBvQTMfi4VqgMY/byTljoGi3MEVcM 1iDg== X-Gm-Message-State: AKGB3mKp/WCSsVdFssMubEQHCqBraMyvL7/kcL0ZBHCCovmMal20Kbn8 eMIDTt2NuRXU2b15ERpn7W3fsNKxmGw= X-Google-Smtp-Source: ACJfBovcFXJ2yaKJM2q2R076DMZIMx6OcgrVbeMOSuyAyvddsfnPff1QLUp1ZMkDHU7cyzQyGha65Q== X-Received: by 10.99.140.73 with SMTP id q9mr16305767pgn.224.1515637417214; Wed, 10 Jan 2018 18:23:37 -0800 (PST) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id e12sm33545939pgu.81.2018.01.10.18.23.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jan 2018 18:23:36 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 18:22:01 -0800 Message-Id: <1515637324-96034-19-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1515637324-96034-1-git-send-email-mjc@sifive.com> References: <1515637324-96034-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 107 +++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_prci.h | 43 +++++++++++++++++ 2 files changed, 150 insertions(+) create mode 100644 hw/riscv/sifive_prci.c create mode 100644 include/hw/riscv/sifive_prci.h diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c new file mode 100644 index 0000000..5c27696 --- /dev/null +++ b/hw/riscv/sifive_prci.c @@ -0,0 +1,107 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2017 SiFive, Inc. + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_prci.h" + +/* currently implements enough to mock freedom-e-sdk BSP clock programming */ + +static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) +{ + if (addr == 0 /* PRCI_HFROSCCFG */) { + return 1 << 31; /* ROSC_RDY */ + } + if (addr == 8 /* PRCI_PLLCFG */) { + return 1 << 31; /* PLL_LOCK */ + } + hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + /* discard writes */ +} + +static const MemoryRegionOps sifive_prci_ops = { + .read = sifive_prci_read, + .write = sifive_prci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_prci_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_prci_init(Object *obj) +{ + SiFivePRCIState *s = SIFIVE_PRCI(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, + TYPE_SIFIVE_PRCI, 0x8000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void sifive_prci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_prci_properties; +} + +static const TypeInfo sifive_prci_info = { + .name = TYPE_SIFIVE_PRCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFivePRCIState), + .instance_init = sifive_prci_init, + .class_init = sifive_prci_class_init, +}; + +static void sifive_prci_register_types(void) +{ + type_register_static(&sifive_prci_info); +} + +type_init(sifive_prci_register_types) + + +/* + * Create PRCI device. + */ +DeviceState *sifive_prci_create(hwaddr addr) +{ + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h new file mode 100644 index 0000000..0e032e5 --- /dev/null +++ b/include/hw/riscv/sifive_prci.h @@ -0,0 +1,43 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_SIFIVE_PRCI_H +#define HW_SIFIVE_PRCI_H + +#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" + +#define SIFIVE_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) + +typedef struct SiFivePRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; +} SiFivePRCIState; + +DeviceState *sifive_prci_create(hwaddr addr); + +#endif