| Message ID | 1519324303-5674-6-git-send-email-aleksandar.markovic@rt-rk.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Aleksandar Markovic <aleksandar.markovic@rt-rk.com> writes: > From: Miodrag Dinic <miodrag.dinic@mips.com> > > While testing mttcg VP0 could get stuck in a loop waiting for other > VPs to come up (which never actually happens). To fix this, kick VPs > while they are being powered up by Cluster Power Controller in an > async task which is triggered once the host thread is being spawned. > > Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com> > Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> > Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > hw/misc/mips_cpc.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c > index 6d34574..712d842 100644 > --- a/hw/misc/mips_cpc.c > +++ b/hw/misc/mips_cpc.c > @@ -30,6 +30,14 @@ static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc) > return (1ULL << cpc->num_vp) - 1; > } > > +static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) > +{ > + MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr; > + > + cpu_reset(cs); > + cpc->vp_running |= 1ULL << cs->cpu_index; > +} > + > static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) > { > CPUState *cs = first_cpu; > @@ -37,8 +45,13 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) > CPU_FOREACH(cs) { > uint64_t i = 1ULL << cs->cpu_index; > if (i & vp_run & ~cpc->vp_running) { > - cpu_reset(cs); > - cpc->vp_running |= i; > + /* > + * To avoid racing with a CPU we are just kicking off. > + * We do the final bit of preparation for the work in > + * the target CPUs context. > + */ > + async_safe_run_on_cpu(cs, mips_cpu_reset_async_work, > + RUN_ON_CPU_HOST_PTR(cpc)); > } > } > } -- Alex Bennée
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index 6d34574..712d842 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips_cpc.c @@ -30,6 +30,14 @@ static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc) return (1ULL << cpc->num_vp) - 1; } +static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) +{ + MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr; + + cpu_reset(cs); + cpc->vp_running |= 1ULL << cs->cpu_index; +} + static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) { CPUState *cs = first_cpu; @@ -37,8 +45,13 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) CPU_FOREACH(cs) { uint64_t i = 1ULL << cs->cpu_index; if (i & vp_run & ~cpc->vp_running) { - cpu_reset(cs); - cpc->vp_running |= i; + /* + * To avoid racing with a CPU we are just kicking off. + * We do the final bit of preparation for the work in + * the target CPUs context. + */ + async_safe_run_on_cpu(cs, mips_cpu_reset_async_work, + RUN_ON_CPU_HOST_PTR(cpc)); } } }