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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id u9sm1769551pgb.11.2018.02.22.16.14.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Feb 2018 16:14:49 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 23 Feb 2018 13:12:08 +1300 Message-Id: <1519344729-73482-23-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1519344729-73482-1-git-send-email-mjc@sifive.com> References: <1519344729-73482-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v6 22/23] SiFive Freedom U500 RISC-V Machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark --- hw/riscv/sifive_u500.c | 339 +++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u500.h | 69 +++++++++ 2 files changed, 408 insertions(+) create mode 100644 hw/riscv/sifive_u500.c create mode 100644 include/hw/riscv/sifive_u500.h diff --git a/hw/riscv/sifive_u500.c b/hw/riscv/sifive_u500.c new file mode 100644 index 0000000..3ae413e --- /dev/null +++ b/hw/riscv/sifive_u500.c @@ -0,0 +1,339 @@ +/* + * QEMU RISC-V Board Compatible with SiFive U500 SDK + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017 SiFive, Inc. + * + * This provides a RISC-V Board compatible with the the SiFive U500 SDK + * + * 0) UART + * 1) CLINT (Core Level Interruptor) + * 2) PLIC (Platform Level Interrupt Controller) + * + * This board currently uses a hardcoded devicetree that indicates one hart. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/char/serial.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_plic.h" +#include "hw/riscv/sifive_clint.h" +#include "hw/riscv/sifive_uart.h" +#include "hw/riscv/sifive_prci.h" +#include "hw/riscv/sifive_u500.h" +#include "chardev/char.h" +#include "sysemu/arch_init.h" +#include "sysemu/device_tree.h" +#include "exec/address-spaces.h" +#include "elf.h" + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} sifive_u500_memmap[] = { + [SIFIVE_U500_DEBUG] = { 0x0, 0x100 }, + [SIFIVE_U500_MROM] = { 0x1000, 0x2000 }, + [SIFIVE_U500_CLINT] = { 0x2000000, 0x10000 }, + [SIFIVE_U500_PLIC] = { 0xc000000, 0x4000000 }, + [SIFIVE_U500_UART0] = { 0x10013000, 0x1000 }, + [SIFIVE_U500_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U500_DRAM] = { 0x80000000, 0x0 }, +}; + +static uint64_t identity_translate(void *opaque, uint64_t addr) +{ + return addr; +} + +static uint64_t load_kernel(const char *kernel_filename) +{ + uint64_t kernel_entry, kernel_high; + + if (load_elf(kernel_filename, identity_translate, NULL, + &kernel_entry, NULL, &kernel_high, + 0, ELF_MACHINE, 1, 0) < 0) { + error_report("qemu: could not load kernel '%s'", kernel_filename); + exit(1); + } + return kernel_entry; +} + +static void create_fdt(SiFiveU500State *s, const struct MemmapEntry *memmap, + uint64_t mem_size, const char *cmdline) +{ + void *fdt; + int cpu; + uint32_t *cells; + char *nodename; + uint32_t plic_phandle; + + fdt = s->fdt = create_device_tree(&s->fdt_size); + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); + qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + + qemu_fdt_add_subnode(fdt, "/soc"); + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc"); + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + + nodename = g_strdup_printf("/memory@%lx", + (long)memmap[SIFIVE_U500_DRAM].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + memmap[SIFIVE_U500_DRAM].base >> 32, memmap[SIFIVE_U500_DRAM].base, + mem_size >> 32, mem_size); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); + g_free(nodename); + + qemu_fdt_add_subnode(fdt, "/cpus"); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + + for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { + nodename = g_strdup_printf("/cpus/cpu@%d", cpu); + char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); + char *isa = riscv_isa_string(&s->soc.harts[cpu]); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000); + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); + qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); + qemu_fdt_add_subnode(fdt, intc); + qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); + qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); + qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); + g_free(isa); + g_free(intc); + g_free(nodename); + } + + cells = g_new0(uint32_t, s->soc.num_harts * 4); + for (cpu = 0; cpu < s->soc.num_harts; cpu++) { + nodename = + g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); + uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); + cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); + g_free(nodename); + } + nodename = g_strdup_printf("/soc/clint@%lx", + (long)memmap[SIFIVE_U500_CLINT].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U500_CLINT].base, + 0x0, memmap[SIFIVE_U500_CLINT].size); + qemu_fdt_setprop(fdt, nodename, "interrupts-extended", + cells, s->soc.num_harts * sizeof(uint32_t) * 4); + g_free(cells); + g_free(nodename); + + cells = g_new0(uint32_t, s->soc.num_harts * 4); + for (cpu = 0; cpu < s->soc.num_harts; cpu++) { + nodename = + g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); + uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); + cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); + g_free(nodename); + } + nodename = g_strdup_printf("/soc/interrupt-controller@%lx", + (long)memmap[SIFIVE_U500_PLIC].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(fdt, nodename, "interrupts-extended", + cells, s->soc.num_harts * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U500_PLIC].base, + 0x0, memmap[SIFIVE_U500_PLIC].size); + qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); + qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); + qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4); + qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2); + qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2); + plic_phandle = qemu_fdt_get_phandle(fdt, nodename); + g_free(cells); + g_free(nodename); + + nodename = g_strdup_printf("/uart@%lx", + (long)memmap[SIFIVE_U500_UART0].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U500_UART0].base, + 0x0, memmap[SIFIVE_U500_UART0].size); + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); + + qemu_fdt_add_subnode(fdt, "/chosen"); + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); + g_free(nodename); +} + +static void riscv_sifive_u500_init(MachineState *machine) +{ + const struct MemmapEntry *memmap = sifive_u500_memmap; + + SiFiveU500State *s = g_new0(SiFiveU500State, 1); + MemoryRegion *sys_memory = get_system_memory(); + MemoryRegion *main_mem = g_new(MemoryRegion, 1); + MemoryRegion *boot_rom = g_new(MemoryRegion, 1); + + /* Initialize SOC */ + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); + object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), + &error_abort); + object_property_set_str(OBJECT(&s->soc), TYPE_RISCV_CPU_IMAFDCSU_PRIV_1_10, + "cpu-type", &error_abort); + object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", + &error_abort); + object_property_set_bool(OBJECT(&s->soc), true, "realized", + &error_abort); + + /* register RAM */ + memory_region_init_ram(main_mem, NULL, "riscv.sifive.u500.ram", + machine->ram_size, &error_fatal); + /* for phys mem size check in page table walk */ + memory_region_add_subregion(sys_memory, memmap[SIFIVE_U500_DRAM].base, + main_mem); + + /* create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + + /* boot rom */ + memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u500.bootrom", + 0x10000, &error_fatal); + memory_region_set_readonly(boot_rom, true); + memory_region_add_subregion(sys_memory, 0x0, boot_rom); + + if (machine->kernel_filename) { + load_kernel(machine->kernel_filename); + } + + /* reset vector */ + uint32_t reset_vec[8] = { + 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + 0xf1402573, /* csrr a0, mhartid */ +#if defined(TARGET_RISCV32) + 0x0182a283, /* lw t0, 24(t0) */ +#elif defined(TARGET_RISCV64) + 0x0182b283, /* ld t0, 24(t0) */ +#endif + 0x00028067, /* jr t0 */ + 0x00000000, + memmap[SIFIVE_U500_DRAM].base, /* start: .dword DRAM_BASE */ + 0x00000000, + /* dtb: */ + }; + + /* copy in the reset vector */ + cpu_physical_memory_write(memmap[SIFIVE_U500_MROM].base, + reset_vec, sizeof(reset_vec)); + + /* copy in the device tree */ + qemu_fdt_dumpdtb(s->fdt, s->fdt_size); + cpu_physical_memory_write(memmap[SIFIVE_U500_MROM].base + + sizeof(reset_vec), s->fdt, s->fdt_size); + + /* MMIO */ + s->plic = sifive_plic_create(memmap[SIFIVE_U500_PLIC].base, + (char *)SIFIVE_U500_PLIC_HART_CONFIG, + SIFIVE_U500_PLIC_NUM_SOURCES, + SIFIVE_U500_PLIC_NUM_PRIORITIES, + SIFIVE_U500_PLIC_PRIORITY_BASE, + SIFIVE_U500_PLIC_PENDING_BASE, + SIFIVE_U500_PLIC_ENABLE_BASE, + SIFIVE_U500_PLIC_ENABLE_STRIDE, + SIFIVE_U500_PLIC_CONTEXT_BASE, + SIFIVE_U500_PLIC_CONTEXT_STRIDE, + memmap[SIFIVE_U500_PLIC].size); + sifive_uart_create(sys_memory, memmap[SIFIVE_U500_UART0].base, + serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U500_UART0_IRQ]); + /* sifive_uart_create(sys_memory, memmap[SIFIVE_U500_UART1].base, + serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U500_UART1_IRQ]); */ + sifive_clint_create(memmap[SIFIVE_U500_CLINT].base, + memmap[SIFIVE_U500_CLINT].size, smp_cpus, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); +} + +static int riscv_sifive_u500_sysbus_device_init(SysBusDevice *sysbusdev) +{ + return 0; +} + +static void riscv_sifive_u500_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + k->init = riscv_sifive_u500_sysbus_device_init; +} + +static const TypeInfo riscv_sifive_u500_device = { + .name = TYPE_SIFIVE_U500, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveU500State), + .class_init = riscv_sifive_u500_class_init, +}; + +static void riscv_sifive_u500_register_types(void) +{ + type_register_static(&riscv_sifive_u500_device); +} + +type_init(riscv_sifive_u500_register_types); + +static void riscv_sifive_u500_machine_init(MachineClass *mc) +{ + mc->desc = "RISC-V Board compatible with SiFive U500 SDK"; + mc->init = riscv_sifive_u500_init; + mc->max_cpus = 1; +} + +DEFINE_MACHINE("sifive_u500", riscv_sifive_u500_machine_init) diff --git a/include/hw/riscv/sifive_u500.h b/include/hw/riscv/sifive_u500.h new file mode 100644 index 0000000..1e0486f --- /dev/null +++ b/include/hw/riscv/sifive_u500.h @@ -0,0 +1,69 @@ +/* + * SiFive U500 series machine interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_SIFIVE_U500_H +#define HW_SIFIVE_U500_H + +#define TYPE_SIFIVE_U500 "riscv.sifive_u500" + +#define SIFIVE_U500(obj) \ + OBJECT_CHECK(SiFiveU500State, (obj), TYPE_SIFIVE_U500) + +typedef struct SiFiveU500State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + RISCVHartArrayState soc; + DeviceState *plic; + void *fdt; + int fdt_size; +} SiFiveU500State; + +enum { + SIFIVE_U500_DEBUG, + SIFIVE_U500_MROM, + SIFIVE_U500_CLINT, + SIFIVE_U500_PLIC, + SIFIVE_U500_UART0, + SIFIVE_U500_UART1, + SIFIVE_U500_DRAM +}; + +enum { + SIFIVE_U500_UART0_IRQ = 3, + SIFIVE_U500_UART1_IRQ = 4 +}; + +#define SIFIVE_U500_PLIC_HART_CONFIG "MS" +#define SIFIVE_U500_PLIC_NUM_SOURCES 127 +#define SIFIVE_U500_PLIC_NUM_PRIORITIES 7 +#define SIFIVE_U500_PLIC_PRIORITY_BASE 0x0 +#define SIFIVE_U500_PLIC_PENDING_BASE 0x1000 +#define SIFIVE_U500_PLIC_ENABLE_BASE 0x2000 +#define SIFIVE_U500_PLIC_ENABLE_STRIDE 0x80 +#define SIFIVE_U500_PLIC_CONTEXT_BASE 0x200000 +#define SIFIVE_U500_PLIC_CONTEXT_STRIDE 0x1000 + +#endif