From patchwork Mon Feb 26 22:17:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 10243871 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 382CC602A0 for ; Mon, 26 Feb 2018 22:27:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B79B2A3C6 for ; Mon, 26 Feb 2018 22:27:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0FD742A3CC; Mon, 26 Feb 2018 22:27:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 51C082A3C6 for ; Mon, 26 Feb 2018 22:27:40 +0000 (UTC) Received: from localhost ([::1]:33525 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqRFD-0004Xe-H7 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 26 Feb 2018 17:27:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49449) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqR7p-0006YJ-8U for qemu-devel@nongnu.org; Mon, 26 Feb 2018 17:20:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqR7o-0005BV-0E for qemu-devel@nongnu.org; Mon, 26 Feb 2018 17:20:01 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:42508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eqR7n-0005BC-OP for qemu-devel@nongnu.org; Mon, 26 Feb 2018 17:19:59 -0500 Received: by mail-pl0-x242.google.com with SMTP id 31so10114206ple.9 for ; Mon, 26 Feb 2018 14:19:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0Easii4jB+iEcQtYijRv4xO46C1WyUkG6FYUQDCQu0Q=; b=OUx3UmcEv9Nz05tqtlsyP7BQ/bxFctBqKL6SDoxjDGXWVgjeN5vtWWlrTmewCRKw3A cTdQVX6SkzR6jvICmH0gFcxkutreFSvdWBGx0kGs/rEEi7O7Ux2ApA7YZb3Blt+BdGkG wLXHiA1FIx9Xi7v4s1nxIW1lP1xmdt5ul2ZUQ/7Q9Rn5z+djiUUtLhxqeexh8sLk3XKX 7wC9FIKTJstK5jX4jM6EiFIx6NuUUGoU4f/k+YagfzqnPdF7NjLI3BdriwFWWtu/Tiir evhPK+k2jop9iC2ftPi1rqrc70P/QP8kNcZm91LrTNZE12D5uhYEJzHMt+uoE2schyJz iBcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0Easii4jB+iEcQtYijRv4xO46C1WyUkG6FYUQDCQu0Q=; b=o953mBgmhq93afwRT/8pT8MyQYjY99JAYbT+0PU+rmkBEp1gYF0oDVjlEAzkmyMVY/ Y3ZrP58SAUUh84HdPZ7MiOhVSDBTSzWIeZEgBEvKD/Tn1NLUmaT2c0sX/Vm0+ijURlRi uaSGNyJdIDLQ0aTwVIOmriA/O24rTaYGs9azV1RVc+MSATxFyG6YucMPW44UX2wGTYyS cov4/W/wDh6/AuQNA9vBTigYYPozRW636tz5ms1Wn7IcvVEw2Vv+MpRkb80C2DfZYV/S iPzromdwYYI6G4SKoyxRuXxDc4P1Nlf7IO7Bv7Qr8JGZR80QsWsTifL6acyfSrtIY/gT Tvmw== X-Gm-Message-State: APf1xPBlktgoD5LKuBqGNgvQQit6jvSNLjSFU5TtqscmF1glsU6DJuMf cl8cYcx5E7n6sET++pAgRhpT0nLXLjA= X-Google-Smtp-Source: AH8x225QwzwHqXQM90/zDwpbdxzMb+dKKRK8mHq2pt9eXxTNJZoSBv92Xxqx5HQxndSKEDvur385uQ== X-Received: by 2002:a17:902:7c84:: with SMTP id y4-v6mr11920555pll.305.1519683598713; Mon, 26 Feb 2018 14:19:58 -0800 (PST) Received: from localhost.localdomain (125-237-39-90.jetstream.xtra.co.nz. [125.237.39.90]) by smtp.gmail.com with ESMTPSA id n14sm13592702pfj.154.2018.02.26.14.19.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Feb 2018 14:19:58 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Tue, 27 Feb 2018 11:17:50 +1300 Message-Id: <1519683480-33201-14-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1519683480-33201-1-git-send-email-mjc@sifive.com> References: <1519683480-33201-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v7 13/23] RISC-V HART Array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Holds the state of a heterogenous array of RISC-V hardware threads. Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 89 +++++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/riscv_hart.h | 39 +++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 hw/riscv/riscv_hart.c create mode 100644 include/hw/riscv/riscv_hart.h diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c new file mode 100644 index 0000000..14e3c18 --- /dev/null +++ b/hw/riscv/riscv_hart.c @@ -0,0 +1,89 @@ +/* + * QEMU RISCV Hart Array + * + * Copyright (c) 2017 SiFive, Inc. + * + * Holds the state of a heterogenous array of RISC-V harts + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/riscv_hart.h" + +static Property riscv_harts_props[] = { + DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), + DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void riscv_harts_cpu_reset(void *opaque) +{ + RISCVCPU *cpu = opaque; + cpu_reset(CPU(cpu)); +} + +static void riscv_harts_realize(DeviceState *dev, Error **errp) +{ + RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); + Error *err = NULL; + int n; + + s->harts = g_new0(RISCVCPU, s->num_harts); + + for (n = 0; n < s->num_harts; n++) { + + object_initialize(&s->harts[n], sizeof(RISCVCPU), s->cpu_type); + s->harts[n].env.mhartid = n; + object_property_add_child(OBJECT(s), "harts[*]", OBJECT(&s->harts[n]), + &error_abort); + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]); + object_property_set_bool(OBJECT(&s->harts[n]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + } +} + +static void riscv_harts_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = riscv_harts_props; + dc->realize = riscv_harts_realize; +} + +static void riscv_harts_init(Object *obj) +{ + /* RISCVHartArrayState *s = SIFIVE_COREPLEX(obj); */ +} + +static const TypeInfo riscv_harts_info = { + .name = TYPE_RISCV_HART_ARRAY, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(RISCVHartArrayState), + .instance_init = riscv_harts_init, + .class_init = riscv_harts_class_init, +}; + +static void riscv_harts_register_types(void) +{ + type_register_static(&riscv_harts_info); +} + +type_init(riscv_harts_register_types) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h new file mode 100644 index 0000000..0671d88 --- /dev/null +++ b/include/hw/riscv/riscv_hart.h @@ -0,0 +1,39 @@ +/* + * QEMU RISC-V Hart Array interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Holds the state of a heterogenous array of RISC-V harts + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_RISCV_HART_H +#define HW_RISCV_HART_H + +#define TYPE_RISCV_HART_ARRAY "riscv.hart_array" + +#define RISCV_HART_ARRAY(obj) \ + OBJECT_CHECK(RISCVHartArrayState, (obj), TYPE_RISCV_HART_ARRAY) + +typedef struct RISCVHartArrayState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + uint32_t num_harts; + char *cpu_type; + RISCVCPU *harts; +} RISCVHartArrayState; + +#endif