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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id g16sm14046966pfd.23.2018.03.02.05.54.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Mar 2018 05:54:21 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Sat, 3 Mar 2018 02:51:49 +1300 Message-Id: <1519998711-73430-22-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1519998711-73430-1-git-send-email-mjc@sifive.com> References: <1519998711-73430-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v8 21/23] SiFive Freedom E Series RISC-V Machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This provides a RISC-V Board compatible with the the SiFive Freedom E SDK. The following machine is implemented: - 'sifive_e'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Acked-by: Richard Henderson Signed-off-by: Sagar Karandikar Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark --- hw/riscv/sifive_e.c | 234 ++++++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_e.h | 79 +++++++++++++++ 2 files changed, 313 insertions(+) create mode 100644 hw/riscv/sifive_e.c create mode 100644 include/hw/riscv/sifive_e.h diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c new file mode 100644 index 0000000..19eca36 --- /dev/null +++ b/hw/riscv/sifive_e.c @@ -0,0 +1,234 @@ +/* + * QEMU RISC-V Board Compatible with SiFive Freedom E SDK + * + * Copyright (c) 2017 SiFive, Inc. + * + * Provides a board compatible with the SiFive Freedom E SDK: + * + * 0) UART + * 1) CLINT (Core Level Interruptor) + * 2) PLIC (Platform Level Interrupt Controller) + * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM + * 5) Flash memory emulated as RAM + * + * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. + * The OTP ROM and Flash boot code will be emulated in a future version. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/char/serial.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_plic.h" +#include "hw/riscv/sifive_clint.h" +#include "hw/riscv/sifive_prci.h" +#include "hw/riscv/sifive_uart.h" +#include "hw/riscv/sifive_e.h" +#include "chardev/char.h" +#include "sysemu/arch_init.h" +#include "exec/address-spaces.h" +#include "elf.h" + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} sifive_e_memmap[] = { + [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, + [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, + [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, + [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, + [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, + [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, + [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, + [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, + [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, + [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, + [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, + [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, + [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, + [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, + [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, + [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, + [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, + [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } +}; + +static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) +{ + int i; + for (i = 0; i < (len >> 2); i++) { + stl_phys(&address_space_memory, pa + (i << 2), rom[i]); + } +} + +static uint64_t identity_translate(void *opaque, uint64_t addr) +{ + return addr; +} + +static uint64_t load_kernel(const char *kernel_filename) +{ + uint64_t kernel_entry, kernel_high; + + if (load_elf(kernel_filename, identity_translate, NULL, + &kernel_entry, NULL, &kernel_high, + 0, ELF_MACHINE, 1, 0) < 0) { + error_report("qemu: could not load kernel '%s'", kernel_filename); + exit(1); + } + return kernel_entry; +} + +static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, + uintptr_t offset, uintptr_t length) +{ + MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); + memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); + memory_region_add_subregion(parent, offset, mock_mmio); +} + +static void riscv_sifive_e_init(MachineState *machine) +{ + const struct MemmapEntry *memmap = sifive_e_memmap; + + SiFiveEState *s = g_new0(SiFiveEState, 1); + MemoryRegion *sys_mem = get_system_memory(); + MemoryRegion *main_mem = g_new(MemoryRegion, 1); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + MemoryRegion *xip_mem = g_new(MemoryRegion, 1); + + /* Initialize SOC */ + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); + object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), + &error_abort); + object_property_set_str(OBJECT(&s->soc), SIFIVE_E_CPU, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", + &error_abort); + object_property_set_bool(OBJECT(&s->soc), true, "realized", + &error_abort); + + /* Data Tightly Integrated Memory */ + memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", + memmap[SIFIVE_E_DTIM].size, &error_fatal); + memory_region_add_subregion(sys_mem, + memmap[SIFIVE_E_DTIM].base, main_mem); + + /* Mask ROM */ + memory_region_init_ram(mask_rom, NULL, "riscv.sifive.e.mrom", + memmap[SIFIVE_E_MROM].size, &error_fatal); + memory_region_add_subregion(sys_mem, + memmap[SIFIVE_E_MROM].base, mask_rom); + + /* MMIO */ + s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, + (char *)SIFIVE_E_PLIC_HART_CONFIG, + SIFIVE_E_PLIC_NUM_SOURCES, + SIFIVE_E_PLIC_NUM_PRIORITIES, + SIFIVE_E_PLIC_PRIORITY_BASE, + SIFIVE_E_PLIC_PENDING_BASE, + SIFIVE_E_PLIC_ENABLE_BASE, + SIFIVE_E_PLIC_ENABLE_STRIDE, + SIFIVE_E_PLIC_CONTEXT_BASE, + SIFIVE_E_PLIC_CONTEXT_STRIDE, + memmap[SIFIVE_E_PLIC].size); + sifive_clint_create(memmap[SIFIVE_E_CLINT].base, + memmap[SIFIVE_E_CLINT].size, smp_cpus, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", + memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); + sifive_prci_create(memmap[SIFIVE_E_PRCI].base); + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0", + memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size); + sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, + serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", + memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", + memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); + /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, + serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", + memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", + memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", + memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); + sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", + memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); + + /* Flash memory */ + memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip", + memmap[SIFIVE_E_XIP].size, &error_fatal); + memory_region_set_readonly(xip_mem, true); + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem); + + /* Mask ROM reset vector */ + uint32_t reset_vec[2] = { + 0x204002b7, /* 0x1000: lui t0,0x20400 */ + 0x00028067, /* 0x1004: jr t0 */ + }; + + /* copy in the reset vector */ + copy_le32_to_phys(memmap[SIFIVE_E_MROM].base, reset_vec, sizeof(reset_vec)); + memory_region_set_readonly(mask_rom, true); + + if (machine->kernel_filename) { + load_kernel(machine->kernel_filename); + } +} + +static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) +{ + return 0; +} + +static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + k->init = riscv_sifive_e_sysbus_device_init; +} + +static const TypeInfo riscv_sifive_e_device = { + .name = TYPE_SIFIVE_E, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveEState), + .class_init = riscv_sifive_e_class_init, +}; + +static void riscv_sifive_e_machine_init(MachineClass *mc) +{ + mc->desc = "RISC-V Board compatible with SiFive E SDK"; + mc->init = riscv_sifive_e_init; + mc->max_cpus = 1; +} + +DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) + +static void riscv_sifive_e_register_types(void) +{ + type_register_static(&riscv_sifive_e_device); +} + +type_init(riscv_sifive_e_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h new file mode 100644 index 0000000..0aebc57 --- /dev/null +++ b/include/hw/riscv/sifive_e.h @@ -0,0 +1,79 @@ +/* + * SiFive E series machine interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_E_H +#define HW_SIFIVE_E_H + +#define TYPE_SIFIVE_E "riscv.sifive_e" + +#define SIFIVE_E(obj) \ + OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) + +typedef struct SiFiveEState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + RISCVHartArrayState soc; + DeviceState *plic; +} SiFiveEState; + +enum { + SIFIVE_E_DEBUG, + SIFIVE_E_MROM, + SIFIVE_E_OTP, + SIFIVE_E_CLINT, + SIFIVE_E_PLIC, + SIFIVE_E_AON, + SIFIVE_E_PRCI, + SIFIVE_E_OTP_CTRL, + SIFIVE_E_GPIO0, + SIFIVE_E_UART0, + SIFIVE_E_QSPI0, + SIFIVE_E_PWM0, + SIFIVE_E_UART1, + SIFIVE_E_QSPI1, + SIFIVE_E_PWM1, + SIFIVE_E_QSPI2, + SIFIVE_E_PWM2, + SIFIVE_E_XIP, + SIFIVE_E_DTIM +}; + +enum { + SIFIVE_E_UART0_IRQ = 3, + SIFIVE_E_UART1_IRQ = 4 +}; + +#define SIFIVE_E_PLIC_HART_CONFIG "M" +#define SIFIVE_E_PLIC_NUM_SOURCES 127 +#define SIFIVE_E_PLIC_NUM_PRIORITIES 7 +#define SIFIVE_E_PLIC_PRIORITY_BASE 0x0 +#define SIFIVE_E_PLIC_PENDING_BASE 0x1000 +#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 +#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 +#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 +#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 + +#if defined(TARGET_RISCV32) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 +#elif defined(TARGET_RISCV64) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#endif + +#endif