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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id y6sm39123791pfg.71.2018.03.06.12.45.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Mar 2018 12:45:55 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 7 Mar 2018 09:43:48 +1300 Message-Id: <1520369037-37977-14-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520369037-37977-1-git-send-email-mjc@sifive.com> References: <1520369037-37977-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards more X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar , RISC-V Patches specific Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- include/hw/riscv/spike.h | 4 ++-- include/hw/riscv/virt.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 179b6cf..ed9d1db 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_SPIKE_H -#define HW_SPIKE_H +#ifndef HW_RISCV_SPIKE_H +#define HW_RISCV_SPIKE_H #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 9588909..d22f184 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -16,8 +16,8 @@ * this program. If not, see . */ -#ifndef HW_VIRT_H -#define HW_VIRT_H +#ifndef HW_RISCV_VIRT_H +#define HW_RISCV_VIRT_H typedef struct { RISCVHartArrayState soc;