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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id h15sm334141pfi.56.2018.03.08.20.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Mar 2018 20:14:17 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:12:25 +1300 Message-Id: <1520568765-58189-4-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1520568765-58189-1-git-send-email-mjc@sifive.com> References: <1520568765-58189-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v2 03/23] RISC-V: Make virt board description match spike X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a402856..0055439 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -404,7 +404,7 @@ static const TypeInfo riscv_virt_board_device = { static void riscv_virt_board_machine_init(MachineClass *mc) { - mc->desc = "RISC-V VirtIO Board (Privileged spec v1.10)"; + mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; mc->init = riscv_virt_board_init; mc->max_cpus = 8; /* hardcoded limit in BBL */ }