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[125.237.39.90]) by smtp.gmail.com with ESMTPSA id p1sm3830097pgr.67.2018.03.09.12.21.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 12:21:29 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Sat, 10 Mar 2018 09:20:18 +1300 Message-Id: <1520626818-93348-1-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH] RISC-V: Fix isa string logic bug, use popcount to count bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Michael Clark , Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Palmer Dabbelt Cc: Peter Maydell Signed-off-by: Michael Clark --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4851890..f0d6d1d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -391,7 +391,7 @@ static const TypeInfo riscv_cpu_type_info = { char *riscv_isa_string(RISCVCPU *cpu) { int i; - size_t maxlen = 5 + ctz32(cpu->env.misa); + size_t maxlen = 5 + __builtin_popcountll(cpu->env.misa); char *isa_string = g_new0(char, maxlen); snprintf(isa_string, maxlen, "rv%d", TARGET_LONG_BITS); for (i = 0; i < sizeof(riscv_exts); i++) {