| Message ID | 1520969191-18162-1-git-send-email-luwei.kang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Mar 14, 2018 at 03:26:31AM +0800, Luwei Kang wrote: > Intel processor trace should be disabled when > CPUID.(EAX=14H,ECX=0H).ECX.[bit31] is set. > Generated packets which contain IP payloads will have LIP > values when this bit is set, or IP payloads will have RIP > values. > Currently, The information of CPUID 14H is constant to make > live migration safty and this bit is always 0 in guest even > if host support LIP values. > Guest sees the bit is 0 will expect IP payloads with RIP > values, but the host CPU will generate IP payloads with > LIP values if this bit is set in HW. > To make sure the value of IP payloads correctly, Intel PT > should be disabled when bit[31] is set. > > Signed-off-by: Luwei Kang <luwei.kang@intel.com> Queued, thanks.
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ec1efd3a3c..3c0eda113e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -194,6 +194,8 @@ * bit[02]: Support Single-Range Output scheme; */ #define INTEL_PT_MINIMAL_ECX 0x7 +/* generated packets which contain IP payloads have LIP values */ +#define INTEL_PT_IP_LIP (1 << 31) #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ @@ -4159,7 +4161,8 @@ static int x86_cpu_filter_features(X86CPU *cpu) ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < INTEL_PT_ADDR_RANGES_NUM) || ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != - (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) { + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || + (ecx_0 & INTEL_PT_IP_LIP)) { /* * Processor Trace capabilities aren't configurable, so if the * host can't emulate the capabilities we report on
Intel processor trace should be disabled when CPUID.(EAX=14H,ECX=0H).ECX.[bit31] is set. Generated packets which contain IP payloads will have LIP values when this bit is set, or IP payloads will have RIP values. Currently, The information of CPUID 14H is constant to make live migration safty and this bit is always 0 in guest even if host support LIP values. Guest sees the bit is 0 will expect IP payloads with RIP values, but the host CPU will generate IP payloads with LIP values if this bit is set in HW. To make sure the value of IP payloads correctly, Intel PT should be disabled when bit[31] is set. Signed-off-by: Luwei Kang <luwei.kang@intel.com> --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)