| Message ID | 1521232280-13089-12-git-send-email-alindsay@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 16 March 2018 at 20:31, Aaron Lindsay <alindsay@codeaurora.org> wrote: > It was shifted to the left one bit too few. > > Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 50eaed7..0102357 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -1123,7 +1123,7 @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > uint64_t saved_cycles = pmccntr_op_start(env); > - env->cp15.pmccfiltr_el0 = value & 0x7E000000; > + env->cp15.pmccfiltr_el0 = value & 0xfc000000; > pmccntr_op_finish(env, saved_cycles); > } > I wonder why we got that one wrong. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Strictly speaking, bit 26 (M) should be visible only in the AArch64 view of the register, not the AArch32 one, but that's a separate issue. thanks -- PMM
On Apr 12 17:41, Peter Maydell wrote: > On 16 March 2018 at 20:31, Aaron Lindsay <alindsay@codeaurora.org> wrote: > > It was shifted to the left one bit too few. > > > > Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> > > --- > > target/arm/helper.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/target/arm/helper.c b/target/arm/helper.c > > index 50eaed7..0102357 100644 > > --- a/target/arm/helper.c > > +++ b/target/arm/helper.c > > @@ -1123,7 +1123,7 @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, > > uint64_t value) > > { > > uint64_t saved_cycles = pmccntr_op_start(env); > > - env->cp15.pmccfiltr_el0 = value & 0x7E000000; > > + env->cp15.pmccfiltr_el0 = value & 0xfc000000; > > pmccntr_op_finish(env, saved_cycles); > > } > > > > I wonder why we got that one wrong. > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > Strictly speaking, bit 26 (M) should be visible only in > the AArch64 view of the register, not the AArch32 one, > but that's a separate issue. Right. I addressed this when I added AArch32 access for PMCCFILTR: [PATCH v3 13/22] target/arm: Allow AArch32 access for PMCCFILTR https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg04910.html -Aaron
diff --git a/target/arm/helper.c b/target/arm/helper.c index 50eaed7..0102357 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1123,7 +1123,7 @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { uint64_t saved_cycles = pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 = value & 0x7E000000; + env->cp15.pmccfiltr_el0 = value & 0xfc000000; pmccntr_op_finish(env, saved_cycles); }
It was shifted to the left one bit too few. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)