From patchwork Fri Mar 16 20:31:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lindsay X-Patchwork-Id: 10290261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4A8B4602C2 for ; Fri, 16 Mar 2018 20:45:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 387262909C for ; Fri, 16 Mar 2018 20:45:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D563290A2; Fri, 16 Mar 2018 20:45:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9BAA32909C for ; Fri, 16 Mar 2018 20:45:45 +0000 (UTC) Received: from localhost ([::1]:59531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewwES-0000xG-S7 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 16 Mar 2018 16:45:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44655) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eww1k-0006Ab-RU for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eww1j-0003lj-SZ for qemu-devel@nongnu.org; Fri, 16 Mar 2018 16:32:36 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56608) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eww1b-0003ZA-OP; Fri, 16 Mar 2018 16:32:28 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6A13360C54; Fri, 16 Mar 2018 20:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232346; bh=eG1gJdVM0L+S3BQp9pYDN7H+pP36YyBh7KdF2OSGB2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gQgJUgFp7c+RphSMQR61YiCuuYMu+PpDW9RPXlSZ52WbLOsf4ZMTDmZ7W5AYNx1Il CvB375GcXWVwlYVkja+aeHxqhGJ2TTnfyMHaG+/OqFfug36+kxkCHlma54wIq5BKyC o2bQP1FGw3cXH2G44fNZPAFcWP4+19ThqpocfPks= Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B06CA60F61; Fri, 16 Mar 2018 20:32:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521232337; bh=eG1gJdVM0L+S3BQp9pYDN7H+pP36YyBh7KdF2OSGB2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GFB6/60+mFwpeipSOYAerrn3/pGcxYW+6/dkQRltOP+Z+PzzukFVfm/AKVxQ9d5Dn ANF/Lx8IXq5LMsincQrxBOMmIzFsDMGrSSx5VzgRWOnPgEKpee0fMTPwbr+oeGSED1 WIng1rpSXcFhk2S4pVauhpAnbGo7PoWRC9zsoQ1M= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B06CA60F61 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Fri, 16 Mar 2018 16:31:14 -0400 Message-Id: <1521232280-13089-17-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Adding an array for v7VE+ CP registers was necessary so that PMOVSSET wasn't defined for all v7 processors. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d4f06e6..f5e800e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1241,9 +1241,17 @@ static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + value &= PMU_COUNTER_MASK(env); env->cp15.c9_pmovsr &= ~value; } +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= PMU_COUNTER_MASK(env); + env->cp15.c9_pmovsr |= value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1406,7 +1414,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .writefn = pmcntenclr_write }, { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, - .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .access = PL0_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), .accessfn = pmreg_access, .writefn = pmovsr_write, .raw_writefn = raw_write }, @@ -1592,6 +1600,25 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v7ve_cp_reginfo[] = { + /* Performance monitor registers which are not implemented in v7 before + * v7ve: + */ + { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4943,6 +4970,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, v7ve_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle