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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id j9sm10547364pff.46.2018.04.29.16.19.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Apr 2018 16:19:37 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 30 Apr 2018 11:18:08 +1200 Message-Id: <1525043888-90983-1-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , patches@groups.riscv.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This fixes an issue when disassembling rv128 c.sqsp, where the code erroneously fell through to c.swsp. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Peter Maydell Signed-off-by: Michael Clark Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- disas/riscv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 74ad16eacdd3..ea19f6fbe2b1 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) if (isa == rv128) { op = rv_op_c_sqsp; } else { - op = rv_op_c_fsdsp; break; + op = rv_op_c_fsdsp; } + break; case 6: op = rv_op_c_swsp; break; case 7: if (isa == rv32) {