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[122.58.167.22]) by smtp.gmail.com with ESMTPSA id q62-v6sm55900800pfd.172.2018.05.24.23.26.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 May 2018 23:26:20 -0700 (PDT) From: Michael Clark To: qemu-trivial@nongnu.org, qemu-devel@nongnu.org Date: Fri, 25 May 2018 18:24:48 +1200 Message-Id: <1527229488-49822-1-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH] RISC-V: Correct typo in RV32 perf counters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch enables mhpmcounter3h through mhpmcounter31h on RV32. Previously the RV32 h versions (high 32-bits of 64-bit counters) of these counters would trap with an illegal instruction instead of returning 0 as intended. Reported-by: Richard Henderson Signed-off-by: Michael Clark Reviewed-by: Richard Henderson --- target/riscv/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3abf52453cfc..1f6dc9a85852 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -406,7 +406,7 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) return 0; } #if defined(TARGET_RISCV32) - if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) { + if (csrno >= CSR_MHPMCOUNTER3H && csrno <= CSR_MHPMCOUNTER31H) { return 0; } #endif