From patchwork Tue Jun 19 15:20:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jingqi" X-Patchwork-Id: 10474683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AA4186029B for ; Tue, 19 Jun 2018 15:24:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9AE6428970 for ; Tue, 19 Jun 2018 15:24:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8E92428DC2; Tue, 19 Jun 2018 15:24:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0138F28970 for ; Tue, 19 Jun 2018 15:24:18 +0000 (UTC) Received: from localhost ([::1]:43235 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVIUS-0003Wp-Kr for patchwork-qemu-devel@patchwork.kernel.org; Tue, 19 Jun 2018 11:24:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fVISa-0002Vb-NQ for qemu-devel@nongnu.org; Tue, 19 Jun 2018 11:22:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fVISZ-0004Nh-Em for qemu-devel@nongnu.org; Tue, 19 Jun 2018 11:22:20 -0400 Received: from mga17.intel.com ([192.55.52.151]:5803) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fVISZ-0004IO-3Y for qemu-devel@nongnu.org; Tue, 19 Jun 2018 11:22:19 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Jun 2018 08:22:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,243,1526367600"; d="scan'208";a="50197456" Received: from optiplex-7050.sh.intel.com ([10.239.161.26]) by orsmga007.jf.intel.com with ESMTP; 19 Jun 2018 08:22:16 -0700 From: Liu Jingqi To: imammedo@redhat.com, ehabkost@redhat.com, eblake@redhat.com, pbonzini@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com, rth@twiddle.net, armbru@redhat.com Date: Tue, 19 Jun 2018 23:20:56 +0800 Message-Id: <1529421657-14969-6-git-send-email-jingqi.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529421657-14969-1-git-send-email-jingqi.liu@intel.com> References: <1529421657-14969-1-git-send-email-jingqi.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.151 Subject: [Qemu-devel] [PATCH V1 RESEND 5/6] numa: Extend the command-line to provide memory side cache information X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liu Jingqi , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add -numa hmat-cache option to provide Memory Side Cache Information. These memory attributes help to build Memory Side Cache Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT). Signed-off-by: Liu Jingqi --- numa.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ qapi/misc.json | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 142 insertions(+), 2 deletions(-) diff --git a/numa.c b/numa.c index d475ef2..6c7b865 100644 --- a/numa.c +++ b/numa.c @@ -293,6 +293,72 @@ static void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node, } } +static void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, + Error **errp) +{ + struct numa_hmat_cache_info *hmat_cache; + + if (node->node_id >= nb_numa_nodes) { + error_setg(errp, "Invalid node-id=%" PRIu32 + ", it should be less than %d.", + node->node_id, nb_numa_nodes); + return; + } + if (!numa_info[node->node_id].is_target) { + error_setg(errp, "Invalid node-id=%" PRIu32 + ", it isn't a target proximity domain.", + node->node_id); + return; + } + + if (node->total > MAX_HMAT_CACHE_LEVEL) { + error_setg(errp, "Invalid total=%" PRIu8 + ", it should be less than or equal to %d.", + node->total, MAX_HMAT_CACHE_LEVEL); + return; + } + if (node->level > node->total) { + error_setg(errp, "Invalid level=%" PRIu8 + ", it should be less than or equal to" + " total=%" PRIu8 ".", + node->level, node->total); + return; + } + if (hmat_cache_info[node->node_id][node->level]) { + error_setg(errp, "Duplicate configuration of the side cache for " + "node-id=%" PRIu32 " and level=%" PRIu8 ".", + node->node_id, node->level); + return; + } + + if ((node->level > 1) && + hmat_cache_info[node->node_id][node->level - 1] && + (node->size >= + hmat_cache_info[node->node_id][node->level - 1]->size)) { + error_setg(errp, "Invalid size=0x%" PRIx64 + ", the size of level=%" PRIu8 + " should be less than the size(0x%" PRIx64 + ") of level=%" PRIu8 ".", + node->size, node->level, + hmat_cache_info[node->node_id][node->level - 1]->size, + node->level - 1); + return; + } + + hmat_cache = g_malloc0(sizeof(*hmat_cache)); + + hmat_cache->mem_proximity = node->node_id; + hmat_cache->size = node->size; + hmat_cache->total_levels = node->total; + hmat_cache->level = node->level; + hmat_cache->associativity = node->assoc; + hmat_cache->write_policy = node->policy; + hmat_cache->line_size = node->line; + hmat_cache->num_smbios_handles = 0; + + hmat_cache_info[node->node_id][node->level] = hmat_cache; +} + static void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) { @@ -332,6 +398,12 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp) goto end; } break; + case NUMA_OPTIONS_TYPE_HMAT_CACHE: + parse_numa_hmat_cache(ms, &object->u.hmat_cache, &err); + if (err) { + goto end; + } + break; default: abort(); } diff --git a/qapi/misc.json b/qapi/misc.json index 51bf005..36bbda2 100644 --- a/qapi/misc.json +++ b/qapi/misc.json @@ -2738,10 +2738,12 @@ # # @hmat-lb: memory latency and bandwidth information (Since: 2.13) # +# @hmat-cache: memory side cache information (Since: 2.13) +# # Since: 2.1 ## { 'enum': 'NumaOptionsType', - 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] } + 'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] } ## # @NumaOptions: @@ -2757,7 +2759,8 @@ 'node': 'NumaNodeOptions', 'dist': 'NumaDistOptions', 'cpu': 'NumaCpuOptions', - 'hmat-lb': 'NumaHmatLBOptions' }} + 'hmat-lb': 'NumaHmatLBOptions', + 'hmat-cache': 'NumaHmatCacheOptions' }} ## # @NumaNodeOptions: @@ -2906,6 +2909,71 @@ '*bandwidth': 'uint16' }} ## +# @HmatCacheAssociativity: +# +# Cache associativity in the Memory Side Cache +# Information Structure of HMAT +# +# @none: None +# +# @direct: Direct Mapped +# +# @complex: Complex Cache Indexing (implementation specific) +# +# Since: 2.13 +## +{ 'enum': 'HmatCacheAssociativity', + 'data': [ 'none', 'direct', 'complex' ] } + +## +# @HmatCacheWritePolicy: +# +# Cache write policy in the Memory Side Cache +# Information Structure of HMAT +# +# @none: None +# +# @write-back: Write Back (WB) +# +# @write-through: Write Through (WT) +# +# Since: 2.13 +## +{ 'enum': 'HmatCacheWritePolicy', + 'data': [ 'none', 'write-back', 'write-through' ] } + +## +# @NumaHmatCacheOptions: +# +# Set the memory side cache information for a given memory domain. +# +# @node-id: the memory proximity domain to which the memory belongs. +# +# @size: the size of memory side cache in bytes. +# +# @total: the total cache levels for this memory proximity domain. +# +# @level: the cache level described in this structure. +# +# @assoc: the cache associativity, none/direct-mapped/complex(complex cache indexing). + +# @policy: the write policy, none/write-back/write-through. +# +# @line: the cache Line size in bytes. +# +# Since: 2.13 +## +{ 'struct': 'NumaHmatCacheOptions', + 'data': { + 'node-id': 'uint32', + 'size': 'size', + 'total': 'uint8', + 'level': 'uint8', + 'assoc': 'HmatCacheAssociativity', + 'policy': 'HmatCacheWritePolicy', + 'line': 'uint16' }} + +## # @HostMemPolicy: # # Host memory policy types