From patchwork Fri Jun 29 11:15:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 10496371 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E69226022E for ; Fri, 29 Jun 2018 11:26:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D5623294DE for ; Fri, 29 Jun 2018 11:26:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C9A86294F2; Fri, 29 Jun 2018 11:26:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 38B3B294DE for ; Fri, 29 Jun 2018 11:26:56 +0000 (UTC) Received: from localhost ([::1]:41259 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrYF-0000IK-Ao for patchwork-qemu-devel@patchwork.kernel.org; Fri, 29 Jun 2018 07:26:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36626) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOa-0000Fs-Ba for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOZ-0002k9-2M for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:56 -0400 Received: from foss.arm.com ([217.140.101.70]:39460) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOY-0002iT-OM for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:54 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 150441682; Fri, 29 Jun 2018 04:16:54 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 482FB3F266; Fri, 29 Jun 2018 04:16:51 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:35 +0100 Message-Id: <1530270944-11351-16-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 15/20] kvm: arm/arm64: Allow tuning the physical address size for VM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydel , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, Paolo Bonzini , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Allow specifying the physical address size for a new VM via the kvm_type argument for KVM_CREATE_VM ioctl. This allows us to finalise the stage2 page table format as early as possible and hence perform the right checks on the memory slots without complication. The size is encoded as Log2(PA_Size) in the bits[7:0] of the type field and can encode more information in the future if required. The IPA size is still capped at 40bits. Cc: Marc Zyngier Cc: Christoffer Dall Cc: Peter Maydel Cc: Paolo Bonzini Cc: Radim Krčmář Signed-off-by: Suzuki K Poulose --- arch/arm/include/asm/kvm_mmu.h | 2 ++ arch/arm64/include/asm/kvm_arm.h | 10 +++------- arch/arm64/include/asm/kvm_mmu.h | 2 ++ include/uapi/linux/kvm.h | 10 ++++++++++ virt/kvm/arm/arm.c | 24 ++++++++++++++++++++++-- 5 files changed, 39 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index d86f8dd..bcc3dd9 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -385,6 +385,8 @@ static inline u32 kvm_get_ipa_limit(void) return KVM_PHYS_SHIFT; } +static inline void kvm_config_stage2(struct kvm *kvm, u32 ipa_shift) {} + #endif /* !__ASSEMBLY__ */ #endif /* __ARM_KVM_MMU_H__ */ diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index b02c316..2e90942 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -128,19 +128,15 @@ #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) /* - * We configure the Stage-2 page tables to always restrict the IPA space to be - * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are - * not known to exist and will break with this configuration. + * We configure the Stage-2 page tables based on the requested size of + * IPA for each VM. The default size is set to 40bits and is not allowed + * go below that limit (for backward compatibility). * * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time * (see hyp-init.S). * * VTCR_EL2.SL0 and T0SZ are configured per VM at runtime before switching to * the VM. - * - * Note that when using 4K pages, we concatenate two first level page tables - * together. With 16K pages, we concatenate 16 first level page tables. - * */ #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index b4564d8..f3fb05a3 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -537,5 +537,7 @@ static inline u32 kvm_get_ipa_limit(void) return KVM_PHYS_SHIFT; } +static inline void kvm_config_stage2(struct kvm *kvm, u32 ipa_shift) {} + #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 4df9bb6..fa4cab0 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -751,6 +751,16 @@ struct kvm_ppc_resize_hpt { #define KVM_S390_SIE_PAGE_OFFSET 1 /* + * On arm/arm64, machine type can be used to request the physical + * address size for the VM. Bits [7-0] have been reserved for the + * PA size shift (i.e, log2(PA_Size)). For backward compatibility, + * value 0 implies the default IPA size, which is 40bits. + */ +#define KVM_VM_TYPE_ARM_PHYS_SHIFT_MASK 0xff +#define KVM_VM_TYPE_ARM_PHYS_SHIFT(x) \ + ((x) & KVM_VM_TYPE_ARM_PHYS_SHIFT_MASK) + +/* * ioctls for /dev/kvm fds: */ #define KVM_GET_API_VERSION _IO(KVMIO, 0x00) diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 0d99e67..1085761 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -112,6 +112,25 @@ void kvm_arch_check_processor_compat(void *rtn) } +static int kvm_arch_config_vm(struct kvm *kvm, unsigned long type) +{ + u32 ipa_shift = KVM_VM_TYPE_ARM_PHYS_SHIFT(type); + + /* + * Make sure the size, if specified, is within the range of + * default size and supported maximum limit. + */ + if (ipa_shift) { + if (ipa_shift < KVM_PHYS_SHIFT || ipa_shift > kvm_ipa_limit) + return -EINVAL; + } else { + ipa_shift = KVM_PHYS_SHIFT; + } + + kvm_config_stage2(kvm, ipa_shift); + return 0; +} + /** * kvm_arch_init_vm - initializes a VM data structure * @kvm: pointer to the KVM struct @@ -120,8 +139,9 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) { int ret, cpu; - if (type) - return -EINVAL; + ret = kvm_arch_config_vm(kvm, type); + if (ret) + return ret; kvm->arch.last_vcpu_ran = alloc_percpu(typeof(*kvm->arch.last_vcpu_ran)); if (!kvm->arch.last_vcpu_ran)