From patchwork Thu Aug 9 11:46:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liran Alon X-Patchwork-Id: 10561341 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4EF27157B for ; Thu, 9 Aug 2018 12:16:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3BDB32AF5B for ; Thu, 9 Aug 2018 12:16:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2FD082AF71; Thu, 9 Aug 2018 12:16:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 97B172AF5B for ; Thu, 9 Aug 2018 12:16:37 +0000 (UTC) Received: from localhost ([::1]:50176 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjro-0006pT-Ll for patchwork-qemu-devel@patchwork.kernel.org; Thu, 09 Aug 2018 08:16:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjQP-0005ZB-21 for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:48:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjQM-0007em-El for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:48:17 -0400 Received: from userp2130.oracle.com ([156.151.31.86]:34626) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjQM-0007eT-4j for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:48:14 -0400 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w79BiaMM146030; Thu, 9 Aug 2018 11:48:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2018-07-02; bh=UteMmBsZlXg1GDFUAugPFnN4RjbpNcq4B2w95Ss/k0Y=; b=knqcPvVEXI7pA2bcUXymIV27beJriUV7QrhJ2+a79HH4/G/1Foe6okZc48F64b6bhPIf MaQgjb9WzxPpd8jylNrJSHgTST6YSbRcRKn2Rf4auIn+bfR3PQ7RR1EP8jybky77GVFP RzSegH+/G6HNiZdpM6Op29R34AUDnFxAF4TM+Mf2A2ETM1Qj6bqbM/GwNH4pEDiSnIkU Yx22BMZvkrVOqRgH1ZSFjX9R9RmSJVIftDdrOBkLZoXIbtLk+99BpEJgQBCHkOu5TFSg cr95Lm48GlGI01knbSpBugrJmEQiWwvUq310ognvya4Q3BMxm7QShrR6EtXB+e3EnLht pQ== Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by userp2130.oracle.com with ESMTP id 2kn3jtav7w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 09 Aug 2018 11:48:13 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w79BmCQw008166 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Aug 2018 11:48:12 GMT Received: from abhmp0014.oracle.com (abhmp0014.oracle.com [141.146.116.20]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w79BmCmc031481; Thu, 9 Aug 2018 11:48:12 GMT Received: from liran-pc.ravello.local (/213.57.127.2) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 09 Aug 2018 04:48:11 -0700 From: Liran Alon To: qemu-devel@nongnu.org Date: Thu, 9 Aug 2018 14:46:39 +0300 Message-Id: <1533815202-11967-27-git-send-email-liran.alon@oracle.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533815202-11967-1-git-send-email-liran.alon@oracle.com> References: <1533815202-11967-1-git-send-email-liran.alon@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8979 signatures=668707 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1808090123 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 156.151.31.86 Subject: [Qemu-devel] [PATCH 26/29] vmsvga: Add basic support for display topology X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: habkost@redhat.com, mtosatti@redhat.com, Liran Alon , kraxel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, Leonid Shatz Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Leonid Shatz Report SVGA_CAP_DISPLAY_TOPOLOGY capability and support single legacy screen at fixed offset of (0,0). This is a pre-requesite for supporting PITCHLOCK feature which is required by Linux kernel vmsvga driver (See Linux kernel vmw_driver_load()). Signed-off-by: Leonid Shatz Reviewed-by: Darren Kenny Signed-off-by: Liran Alon --- hw/display/vmware_vga.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index b2f3456357bd..edd336e65005 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -81,6 +81,7 @@ struct vmsvga_state_s { uint32_t num_fifo_regs; uint32_t irq_mask; uint32_t irq_status; + uint32_t display_id; }; #define TYPE_VMWARE_SVGA "vmware-svga" @@ -103,6 +104,9 @@ struct pci_vmsvga_state_s { #define SVGA_ID_1 SVGA_MAKE_ID(1) #define SVGA_ID_2 SVGA_MAKE_ID(2) +/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */ +#define SVGA_ID_INVALID 0xFFFFFFFF + #define SVGA_LEGACY_BASE_PORT 0x4560 #define SVGA_INDEX_PORT 0x0 #define SVGA_VALUE_PORT 0x1 @@ -164,6 +168,15 @@ enum { SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ SVGA_REG_IRQMASK = 33, /* Interrupt mask */ + /* Legacy multi-monitor support */ + SVGA_REG_NUM_GUEST_DISPLAYS = 34, /* Number of guest displays in X/Y direction */ + SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */ + SVGA_REG_DISPLAY_IS_PRIMARY = 36, /* Whether this is a primary display */ + SVGA_REG_DISPLAY_POSITION_X = 37, /* The display position x */ + SVGA_REG_DISPLAY_POSITION_Y = 38, /* The display position y */ + SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ + SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ + /* Guest memory regions */ SVGA_REG_GMR_ID = 41, SVGA_REG_GMR_DESCRIPTOR = 42, @@ -195,6 +208,7 @@ enum { #define SVGA_CAP_MULTIMON (1 << 16) #define SVGA_CAP_PITCHLOCK (1 << 17) #define SVGA_CAP_IRQMASK (1 << 18) +#define SVGA_CAP_DISPLAY_TOPOLOGY (1 << 19) // Legacy multi-monitor support /* * FIFO offsets (seen as an array of 32-bit words) @@ -1227,6 +1241,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) #endif caps |= SVGA_CAP_EXTENDED_FIFO; caps |= SVGA_CAP_IRQMASK; + caps |= SVGA_CAP_DISPLAY_TOPOLOGY; ret = caps; break; @@ -1288,6 +1303,32 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) ret = s->irq_mask; break; + case SVGA_REG_NUM_GUEST_DISPLAYS: + ret = 1; + break; + case SVGA_REG_DISPLAY_ID: + ret = s->display_id; + break; + case SVGA_REG_DISPLAY_IS_PRIMARY: + ret = s->display_id == 0 ? 1 : 0; + break; + case SVGA_REG_DISPLAY_POSITION_X: + case SVGA_REG_DISPLAY_POSITION_Y: + ret = 0; + break; + case SVGA_REG_DISPLAY_WIDTH: + if ((s->display_id == 0) || (s->display_id == SVGA_ID_INVALID)) + ret = s->new_width ? s->new_width : surface_width(surface); + else + ret = 0; + break; + case SVGA_REG_DISPLAY_HEIGHT: + if ((s->display_id == 0) || (s->display_id == SVGA_ID_INVALID)) + ret = s->new_height ? s->new_height : surface_height(surface); + else + ret = 0; + break; + /* Guest memory regions */ case SVGA_REG_GMR_ID: case SVGA_REG_GMR_DESCRIPTOR: @@ -1431,6 +1472,28 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) s->irq_mask = value; break; + /* We support single legacy screen at fixed offset of (0,0) */ + case SVGA_REG_DISPLAY_ID: + s->display_id = value; + break; + case SVGA_REG_NUM_GUEST_DISPLAYS: + case SVGA_REG_DISPLAY_IS_PRIMARY: + case SVGA_REG_DISPLAY_POSITION_X: + case SVGA_REG_DISPLAY_POSITION_Y: + break; + case SVGA_REG_DISPLAY_WIDTH: + if ((s->display_id == 0) && (value <= SVGA_MAX_WIDTH)) { + s->new_width = value; + s->invalidated = 1; + } + break; + case SVGA_REG_DISPLAY_HEIGHT: + if ((s->display_id == 0) && (value <= SVGA_MAX_HEIGHT)) { + s->new_height = value; + s->invalidated = 1; + } + break; + default: if (s->index >= SVGA_SCRATCH_BASE && s->index < SVGA_SCRATCH_BASE + s->scratch_size) { @@ -1534,6 +1597,7 @@ static void vmsvga_reset(DeviceState *dev) s->irq_mask = 0; s->irq_status = 0; s->last_fifo_cursor_count = 0; + s->display_id = SVGA_ID_INVALID; vga_dirty_log_start(&s->vga); } @@ -1568,6 +1632,7 @@ static int vmsvga_post_load(void *opaque, int version_id) s->irq_mask = 0; s->irq_status = 0; s->last_fifo_cursor_count = 0; + s->display_id = SVGA_ID_INVALID; } return 0; @@ -1598,6 +1663,7 @@ static const VMStateDescription vmstate_vmware_vga_internal = { VMSTATE_UINT32_V(irq_mask, struct vmsvga_state_s, 1), VMSTATE_UINT32_V(irq_status, struct vmsvga_state_s, 1), VMSTATE_UINT32_V(last_fifo_cursor_count, struct vmsvga_state_s, 1), + VMSTATE_UINT32_V(display_id, struct vmsvga_state_s, 1), VMSTATE_END_OF_LIST() } };