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[PULL,v4,04/46] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS

Message ID 1535031276-22911-5-git-send-email-aleksandar.markovic@rt-rk.com (mailing list archive)
State New, archived
Headers show
Series [PULL,v4,01/46] target/mips: Add preprocessor constants for nanoMIPS | expand

Commit Message

Aleksandar Markovic Aug. 23, 2018, 1:33 p.m. UTC 
From: Stefan Markovic <smarkovic@wavecomp.com>

Only if Config3.ISA is 3 (microMIPS), the mode should be switched in
cpu_state_reset(). Config3.ISA is 1 for nanoMIPS processors, and no mode
change should happen.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4f95b9a..7fb322b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -21841,8 +21841,8 @@  void cpu_state_reset(CPUMIPSState *env)
         env->CP0_Status |= (1 << CP0St_FR);
     }
 
-    if (env->CP0_Config3 & (1 << CP0C3_ISA)) {
-        /*  microMIPS on reset when Config3.ISA == {1, 3} */
+    if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
+        /*  microMIPS on reset when Config3.ISA is 3 */
         env->hflags |= MIPS_HFLAG_M16;
     }