@@ -43,7 +43,7 @@ CONFIG_USB_MUSB=y
CONFIG_USB_EHCI_SYSBUS=y
CONFIG_PLATFORM_BUS=y
CONFIG_VIRTIO_MMIO=y
-
+CONFIG_PVPANIC_MMIO=y
CONFIG_ARM11MPCORE=y
CONFIG_A9MPCORE=y
CONFIG_A15MPCORE=y
@@ -140,6 +140,7 @@ static const MemMapEntry a15memmap[] = {
[VIRT_UART] = { 0x09000000, 0x00001000 },
[VIRT_RTC] = { 0x09010000, 0x00001000 },
[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
+ [VIRT_PVPANIC_MMIO] = { 0x09020018, 0x00000002 },
[VIRT_GPIO] = { 0x09030000, 0x00001000 },
[VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
[VIRT_SMMU] = { 0x09050000, 0x00020000 },
@@ -798,6 +799,24 @@ static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
g_free(nodename);
}
+static void create_pvpanic_device(const VirtMachineState *vms)
+{
+ char *nodename;
+ hwaddr base = vms->memmap[VIRT_PVPANIC_MMIO].base;
+ hwaddr size = vms->memmap[VIRT_PVPANIC_MMIO].size;
+
+ sysbus_create_simple("pvpanic-mmio", base, NULL);
+
+ nodename = g_strdup_printf("/pvpanic-mmio@%" PRIx64, base);
+ qemu_fdt_add_subnode(vms->fdt, nodename);
+ qemu_fdt_setprop_string(vms->fdt, nodename,
+ "compatible", "pvpanic,mmio");
+ qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
+ 2, base, 2, size);
+ g_free(nodename);
+
+}
+
static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
{
int i;
@@ -1544,6 +1563,8 @@ static void machvirt_init(MachineState *machine)
create_pcie(vms, pic);
+ create_pvpanic_device(vms);
+
create_gpio(vms, pic);
/* Create mmio transports, so the user can create virtio backends
@@ -71,6 +71,7 @@ obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
+obj-$(CONFIG_PVPANIC_MMIO) += pvpanic-mmio.o
obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
new file mode 100644
@@ -0,0 +1,76 @@
+#include "qemu/osdep.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+#include "hw/misc/pvpanic-mmio.h"
+
+#define PVPANIC_MMIO_FEAT_CRASHED 0
+
+#define PVPANIC_MMIO_CRASHED (1 << PVPANIC_MMIO_FEAT_CRASHED)
+
+static void handle_mmio_event(int event)
+{
+ static bool logged;
+
+ if (event & ~PVPANIC_MMIO_CRASHED && !logged) {
+ qemu_log_mask(LOG_GUEST_ERROR, "pvpanic-mmio: unknown event %#x.\n", event);
+ logged = true;
+ }
+
+ if (event & PVPANIC_MMIO_CRASHED) {
+ qemu_system_guest_panicked(NULL);
+ return;
+ }
+}
+
+static uint64_t pvpanic_mmio_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return -1;
+}
+
+static void pvpanic_mmio_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ handle_mmio_event(value);
+}
+
+static const MemoryRegionOps pvpanic_mmio_ops = {
+ .read = pvpanic_mmio_read,
+ .write = pvpanic_mmio_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 2,
+ },
+};
+
+
+static void pvpanic_mmio_initfn(Object *obj)
+{
+ PVPanicState *s = PVPANIC_MMIO_DEVICE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &pvpanic_mmio_ops, s,
+ "pvpanic-mmio", 2);
+ sysbus_init_mmio(sbd, &s->mmio);
+}
+
+static void pvpanic_mmio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static TypeInfo pvpanic_mmio_info = {
+ .name = TYPE_PVPANIC_MMIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PVPanicState),
+ .instance_init = pvpanic_mmio_initfn,
+ .class_init = pvpanic_mmio_class_init,
+};
+
+static void pvpanic_mmio_register_types(void)
+{
+ type_register_static(&pvpanic_mmio_info);
+}
+
+type_init(pvpanic_mmio_register_types)
@@ -70,6 +70,7 @@ enum {
VIRT_MMIO,
VIRT_RTC,
VIRT_FW_CFG,
+ VIRT_PVPANIC_MMIO,
VIRT_PCIE,
VIRT_PCIE_MMIO,
VIRT_PCIE_PIO,
new file mode 100644
@@ -0,0 +1,12 @@
+#ifndef HW_MISC_PVPANIC_H
+#define HW_MISC_PVPANIC_H
+#include "hw/sysbus.h"
+#define TYPE_PVPANIC_MMIO "pvpanic-mmio"
+#define PVPANIC_MMIO_DEVICE(obj) \
+ OBJECT_CHECK(PVPanicState, (obj), TYPE_PVPANIC_MMIO)
+#endif
+
+typedef struct PVPanicState {
+ SysBusDevice parent_obj;
+ MemoryRegion mmio;
+} PVPanicState;