From patchwork Mon Oct 29 11:25:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 10659161 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A9A36174F for ; Mon, 29 Oct 2018 11:36:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98E7E297C8 for ; Mon, 29 Oct 2018 11:36:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8D5AA297E4; Mon, 29 Oct 2018 11:36:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2D370297C8 for ; Mon, 29 Oct 2018 11:36:30 +0000 (UTC) Received: from localhost ([::1]:44816 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH5qP-0000uA-Br for patchwork-qemu-devel@patchwork.kernel.org; Mon, 29 Oct 2018 07:36:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH5i7-0001tl-1x for qemu-devel@nongnu.org; Mon, 29 Oct 2018 07:27:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH5i4-0005KB-Lx for qemu-devel@nongnu.org; Mon, 29 Oct 2018 07:27:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34719 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH5i4-0004q2-32 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 07:27:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 869D71A227C; Mon, 29 Oct 2018 12:27:31 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6660E1A2278; Mon, 29 Oct 2018 12:27:31 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 12:25:20 +0100 Message-Id: <1540812328-16163-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540812328-16163-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540812328-16163-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v8 12/20] target/mips: Add emulation of MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jancraig@amazon.com, smarkovic@wavecomp.com, richard.henderson@linaro.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Craig Janeczek Add support for emulating the S32I2M and S32M2I MXU instructions. This commit also contains utility functions for reading/writing to MXU registers. This is required for overall MXU instruction support. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 91 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 85 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a98de28..8b91676 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2569,6 +2569,36 @@ static inline void gen_store_srsgpr (int from, int to) } } +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg == 0) { + tcg_gen_movi_tl(t, 0); + } else if (reg <= 15) { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg > 0 && reg <= 15) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + +/* MXU control register moves. */ +static inline void gen_load_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(t, mxu_CR); +} + +static inline void gen_store_mxu_cr(TCGv t) +{ + /* TODO: Add handling of RW rules for MXU_CR. */ + tcg_gen_mov_tl(mxu_CR, t); +} + + /* Tests */ static inline void gen_save_pc(target_ulong pc) { @@ -24011,6 +24041,59 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) /* + * S32I2M XRa, rb - Register move from GRF to XRF + */ +static void gen_mxu_s32i2m(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 = tcg_temp_new(); + + XRa = extract32(ctx->opcode, 6, 5); + Rb = extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, Rb); + if (XRa <= 15) { + gen_store_mxu_gpr(t0, XRa); + } else if (XRa == 16) { + gen_store_mxu_cr(t0); + } + + tcg_temp_free(t0); +} + +/* + * S32M2I XRa, rb - Register move from XRF to GRF + */ +static void gen_mxu_s32m2i(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 = tcg_temp_new(); + + XRa = extract32(ctx->opcode, 6, 5); + Rb = extract32(ctx->opcode, 16, 5); + + if (XRa <= 15) { + gen_load_mxu_gpr(t0, XRa); + } else if (XRa == 16) { + gen_load_mxu_cr(t0); + } + + gen_store_gpr(t0, Rb); + + tcg_temp_free(t0); +} + + +/* + * Decoding engine for MXU + * ======================= + */ + +/* * * Decode MXU pool00 * @@ -25089,14 +25172,10 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S32M2I: - /* TODO: Implement emulation of S32M2I instruction. */ - MIPS_INVAL("OPC_MXU_S32M2I"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s32m2i(ctx); break; case OPC_MXU_S32I2M: - /* TODO: Implement emulation of S32I2M instruction. */ - MIPS_INVAL("OPC_MXU_S32I2M"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s32i2m(ctx); break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */