| Message ID | 154394078336.28192.11850479111762649553.stgit@gimli.home (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | pcie: Enhanced link speed and width support | expand |
Hi, On 12/4/18 5:26 PM, Alex Williamson wrote: > Add fields allowing the PCIe link speed and width of a PCIESlot to > be configured, with an instance_post_init callback on the root port > parent class to set defaults. This allows child classes to set these > via properties or via their own instance_init callback, without > requiring all implementions to support arbitrary user selected values. > > Cc: Michael S. Tsirkin <mst@redhat.com> > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> > Tested-by: Geoffrey McRae <geoff@hostfission.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Thanks Eric > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > --- > hw/pci-bridge/pcie_root_port.c | 14 ++++++++++++++ > include/hw/pci/pcie_port.h | 4 ++++ > 2 files changed, 18 insertions(+) > > diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c > index 45f9e8cd4a36..34ad76743c44 100644 > --- a/hw/pci-bridge/pcie_root_port.c > +++ b/hw/pci-bridge/pcie_root_port.c > @@ -140,6 +140,19 @@ static Property rp_props[] = { > DEFINE_PROP_END_OF_LIST() > }; > > +static void rp_instance_post_init(Object *obj) > +{ > + PCIESlot *s = PCIE_SLOT(obj); > + > + if (!s->speed) { > + s->speed = QEMU_PCI_EXP_LNK_2_5GT; > + } > + > + if (!s->width) { > + s->width = QEMU_PCI_EXP_LNK_X1; > + } > +} > + > static void rp_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -157,6 +170,7 @@ static void rp_class_init(ObjectClass *klass, void *data) > static const TypeInfo rp_info = { > .name = TYPE_PCIE_ROOT_PORT, > .parent = TYPE_PCIE_SLOT, > + .instance_post_init = rp_instance_post_init, > .class_init = rp_class_init, > .abstract = true, > .class_size = sizeof(PCIERootPortClass), > diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h > index 0736014bfdb4..df242a0cafff 100644 > --- a/include/hw/pci/pcie_port.h > +++ b/include/hw/pci/pcie_port.h > @@ -49,6 +49,10 @@ struct PCIESlot { > /* pci express switch port with slot */ > uint8_t chassis; > uint16_t slot; > + > + PCIExpLinkSpeed speed; > + PCIExpLinkWidth width; > + > QLIST_ENTRY(PCIESlot) next; > }; > > >
diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 45f9e8cd4a36..34ad76743c44 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -140,6 +140,19 @@ static Property rp_props[] = { DEFINE_PROP_END_OF_LIST() }; +static void rp_instance_post_init(Object *obj) +{ + PCIESlot *s = PCIE_SLOT(obj); + + if (!s->speed) { + s->speed = QEMU_PCI_EXP_LNK_2_5GT; + } + + if (!s->width) { + s->width = QEMU_PCI_EXP_LNK_X1; + } +} + static void rp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -157,6 +170,7 @@ static void rp_class_init(ObjectClass *klass, void *data) static const TypeInfo rp_info = { .name = TYPE_PCIE_ROOT_PORT, .parent = TYPE_PCIE_SLOT, + .instance_post_init = rp_instance_post_init, .class_init = rp_class_init, .abstract = true, .class_size = sizeof(PCIERootPortClass), diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 0736014bfdb4..df242a0cafff 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -49,6 +49,10 @@ struct PCIESlot { /* pci express switch port with slot */ uint8_t chassis; uint16_t slot; + + PCIExpLinkSpeed speed; + PCIExpLinkWidth width; + QLIST_ENTRY(PCIESlot) next; };