From patchwork Thu Mar 21 18:40:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandra Loosemore X-Patchwork-Id: 10864209 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46A951669 for ; Thu, 21 Mar 2019 18:55:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 24AB62A385 for ; Thu, 21 Mar 2019 18:55:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 187642A3C0; Thu, 21 Mar 2019 18:55:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 30C3B2A385 for ; Thu, 21 Mar 2019 18:55:39 +0000 (UTC) Received: from localhost ([127.0.0.1]:45217 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h72qo-0002hb-Eq for patchwork-qemu-devel@patchwork.kernel.org; Thu, 21 Mar 2019 14:55:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:49788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h72mU-0007gz-Oi for qemu-devel@nongnu.org; Thu, 21 Mar 2019 14:51:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h72cW-0007Lp-HF for qemu-devel@nongnu.org; Thu, 21 Mar 2019 14:40:54 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:63225) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h72cV-0007FX-FX for qemu-devel@nongnu.org; Thu, 21 Mar 2019 14:40:51 -0400 Received: from svr-orw-mbx-03.mgc.mentorg.com ([147.34.90.203]) by relay1.mentorg.com with esmtps (TLSv1.2:ECDHE-RSA-AES256-SHA384:256) id 1h72cQ-0006pZ-FZ from Sandra_Loosemore@mentor.com ; Thu, 21 Mar 2019 11:40:46 -0700 Received: from anura.Home (147.34.91.1) by svr-orw-mbx-03.mgc.mentorg.com (147.34.90.203) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Thu, 21 Mar 2019 11:40:43 -0700 From: Sandra Loosemore To: Date: Thu, 21 Mar 2019 12:40:29 -0600 Message-ID: <1553193630-28611-2-git-send-email-sandra@codesourcery.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553193630-28611-1-git-send-email-sandra@codesourcery.com> References: <1553193630-28611-1-git-send-email-sandra@codesourcery.com> MIME-Version: 1.0 X-ClientProxiedBy: SVR-ORW-MBX-06.mgc.mentorg.com (147.34.90.206) To svr-orw-mbx-03.mgc.mentorg.com (147.34.90.203) X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 192.94.38.131 Subject: [Qemu-devel] [PATCH v6 1/2] Add generic Nios II board. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, crwulff@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for a generic MMU-less Nios II board that can be used e.g. for bare-metal compiler testing with the linker script and startup code provided by libgloss. Nios II booting is also tweaked so that bare-metal binaries start executing in RAM starting at 0x00000000, rather than an alias at 0xc0000000, which allows features such as unwinding to work when binaries are linked to start at the beginning of the address space. The generic_nommu.c parts are based on code by Andrew Jenner, which was in turn based on code by Marek Vasut. Originally by Marek Vasut and Andrew Jenner. Signed-off-by: Sandra Loosemore Signed-off-by: Julian Brown Signed-off-by: Andrew Jenner Signed-off-by: Marek Vasut --- default-configs/nios2-softmmu.mak | 1 + hw/nios2/Kconfig | 4 ++ hw/nios2/Makefile.objs | 1 + hw/nios2/boot.c | 17 ++++--- hw/nios2/generic_nommu.c | 104 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 121 insertions(+), 6 deletions(-) create mode 100644 hw/nios2/generic_nommu.c diff --git a/default-configs/nios2-softmmu.mak b/default-configs/nios2-softmmu.mak index e11dc54..e130d02 100644 --- a/default-configs/nios2-softmmu.mak +++ b/default-configs/nios2-softmmu.mak @@ -3,3 +3,4 @@ # Boards: # CONFIG_NIOS2_10M50=y +CONFIG_NIOS2_GENERIC_NOMMU=y diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig index ab953e0..b10ea64 100644 --- a/hw/nios2/Kconfig +++ b/hw/nios2/Kconfig @@ -4,5 +4,9 @@ config NIOS2_10M50 select SERIAL select ALTERA_TIMER +config NIOS2_GENERIC_NOMMU + bool + select NIOS2 + config NIOS2 bool diff --git a/hw/nios2/Makefile.objs b/hw/nios2/Makefile.objs index 89a419a..3e01798 100644 --- a/hw/nios2/Makefile.objs +++ b/hw/nios2/Makefile.objs @@ -1,2 +1,3 @@ obj-y = boot.o cpu_pic.o obj-$(CONFIG_NIOS2_10M50) += 10m50_devboard.o +obj-$(CONFIG_NIOS2_GENERIC_NOMMU) += generic_nommu.o diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index 5f0ab2f..771877d 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -138,7 +138,6 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base, if (kernel_filename) { int kernel_size, fdt_size; uint64_t entry, low, high; - uint32_t base32; int big_endian = 0; #ifdef TARGET_WORDS_BIGENDIAN @@ -149,16 +148,22 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base, kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &entry, &low, &high, big_endian, EM_ALTERA_NIOS2, 0, 0); - base32 = entry; - if (base32 == 0xc0000000) { + if ((uint32_t)entry == 0xc0000000) { + /* The Nios II processor reference guide documents that the + kernel is placed at virtual memory address 0xc0000000, + and we've got something that points there. Reload it + and adjust the entry to get the address in physical RAM. */ kernel_size = load_elf(kernel_filename, NULL, translate_kernel_address, NULL, &entry, NULL, NULL, big_endian, EM_ALTERA_NIOS2, 0, 0); + boot_info.bootstrap_pc = ddr_base + 0xc0000000 + + (entry & 0x07ffffff); + } + else { + /* Use the entry point in the ELF image. */ + boot_info.bootstrap_pc = (uint32_t)entry; } - - /* Always boot into physical ram. */ - boot_info.bootstrap_pc = ddr_base + 0xc0000000 + (entry & 0x07ffffff); /* If it wasn't an ELF image, try an u-boot image. */ if (kernel_size < 0) { diff --git a/hw/nios2/generic_nommu.c b/hw/nios2/generic_nommu.c new file mode 100644 index 0000000..af8983a --- /dev/null +++ b/hw/nios2/generic_nommu.c @@ -0,0 +1,104 @@ +/* + * Generic simulator target with no MMU or devices. This emulation is + * compatible with the libgloss qemu-hosted.ld linker script for using + * QEMU as an instruction set simulator. + * + * Copyright (c) 2018-2019 Mentor Graphics + * + * Copyright (c) 2016 Marek Vasut + * + * Based on LabX device code + * + * Copyright (c) 2012 Chris Wulff + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "cpu.h" + +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "hw/char/serial.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" +#include "exec/memory.h" +#include "exec/address-spaces.h" +#include "qemu/config-file.h" + +#include "boot.h" + +#define BINARY_DEVICE_TREE_FILE "generic-nommu.dtb" + +static void nios2_generic_nommu_init(MachineState *machine) +{ + Nios2CPU *cpu; + MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *phys_tcm = g_new(MemoryRegion, 1); + MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1); + MemoryRegion *phys_ram = g_new(MemoryRegion, 1); + MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1); + ram_addr_t tcm_base = 0x0; + ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ + ram_addr_t ram_base = 0x10000000; + ram_addr_t ram_size = 0x08000000; + + /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ + memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size, + &error_abort); + memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias", + phys_tcm, 0, tcm_size); + memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm); + memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base, + phys_tcm_alias); + + /* Physical DRAM with alias at 0xc0000000 */ + memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size, + &error_abort); + memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias", + phys_ram, 0, ram_size); + memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, + phys_ram_alias); + + cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); + + /* Remove MMU */ + cpu->mmu_present = false; + + /* Reset vector is the first 32 bytes of RAM. */ + cpu->reset_addr = ram_base; + + /* The libgloss linker script doesn't include an exception vector, + so use the reset address. Boo. */ + cpu->exception_addr = cpu->reset_addr; + + /* The linker script does have a TLB miss memory region declared, + but this should never be used with no MMU. */ + cpu->fast_tlb_miss_addr = 0x7fff400; + + nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename, + BINARY_DEVICE_TREE_FILE, NULL); +} + +static void nios2_generic_nommu_machine_init(struct MachineClass *mc) +{ + mc->desc = "Generic NOMMU Nios II design"; + mc->init = nios2_generic_nommu_init; +} + +DEFINE_MACHINE("nios2-generic-nommu", nios2_generic_nommu_machine_init);