From patchwork Mon Mar 25 14:52:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateja Marjanovic X-Patchwork-Id: 10869475 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3BA1F14DE for ; Mon, 25 Mar 2019 14:58:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1AE0F293FC for ; Mon, 25 Mar 2019 14:58:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0F2D129415; Mon, 25 Mar 2019 14:58:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BA4DA293FC for ; Mon, 25 Mar 2019 14:58:28 +0000 (UTC) Received: from localhost ([127.0.0.1]:43799 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8R3U-0000WE-2F for patchwork-qemu-devel@patchwork.kernel.org; Mon, 25 Mar 2019 10:58:28 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8QzA-0004qk-Am for qemu-devel@nongnu.org; Mon, 25 Mar 2019 10:54:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h8Qz9-0003w0-BT for qemu-devel@nongnu.org; Mon, 25 Mar 2019 10:54:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:50305 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h8Qz9-0003vO-1s for qemu-devel@nongnu.org; Mon, 25 Mar 2019 10:53:59 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 175DD1A2067; Mon, 25 Mar 2019 15:52:55 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.97]) by mail.rt-rk.com (Postfix) with ESMTPSA id E1A0C1A206F; Mon, 25 Mar 2019 15:52:54 +0100 (CET) From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 15:52:44 +0100 Message-Id: <1553525566-14913-6-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553525566-14913-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1553525566-14913-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 5/7] target/mips: Eliminate unreachable case for MSA instructions copy_u X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Mateja Marjanovic The copy_u instruction doesn't support doublewords, and supports words only if the CPU is MIPS64 [1] (page 138), for MIPS32 it supports only byte and halfword [2] (page 138). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module [2] MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module Signed-off-by: Mateja Marjanovic --- target/mips/msa_helper.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index ac5d41e..f368f79 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1482,13 +1482,10 @@ void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, case DF_HALF: env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n]; break; +#ifdef TARGET_MIPS64 case DF_WORD: env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; break; -#ifdef TARGET_MIPS64 - case DF_DOUBLE: - env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n]; - break; #endif default: assert(0);